tag: Synopsys

Re-Architecting AI For Power
By Brian Bailey - 14 Aug, 2025 - Comments: 0

The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

Reliable Training Data Paramount To AI Model Success
By Ann Mutschler - 14 Aug, 2025 - Comments: 0

AI systems are increasingly being integrated into safety- and mission-critical applications ranging from automotive to health care and industrial IoT, stepping up the need for training data that is reliable, secure, and which is generated from trusted sources. AI activity is growing exponentially, as everybody tries to figure out how to apply it to their domain, application, or workload. In ... » read more

Building An AI Chip: Pre Silicon Planning
By Synopsys - 13 Aug, 2025 - Comments: 0

This white paper highlights the challenges of AI chip design, including balancing performance, cost, and power efficiency. It emphasizes the importance of early architecture exploration to avoid costly design revisions and ensure optimal power-performance trade-offs. The paper underscores the need for secure, efficient, and scalable IP solutions to meet the evolving demands of AI applications, ... » read more

Best Practices to Optimize Infrastructure for Simulations
By Ansys - 13 Aug, 2025 - Comments: 0

Our Best Practices Guide equips you with expert strategies for leveraging high-performance computing (HPC) to maximize Ansys workload efficiency and overcome common challenges. As simulation complexity increases, a robust computing infrastructure is essential for rapid and large-scale modeling. Modern HPC systems provide: High-core-count CPUs for superior memory and compute perfo... » read more

Transforming Test For Co-packaged Optics
By Laura Peters - 12 Aug, 2025 - Comments: 0

Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day. To enable this change in production manufacturi... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
By Gregory Haley - 12 Aug, 2025 - Comments: 1

As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

Test Hyperconvergence In Semiconductor Development
By Pawini Mahajan - 12 Aug, 2025 - Comments: 0

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who developed a set of test patterns for the manufacturing floor. As this process became more automated and chips became more complicated, test considerations crept into the development flow and design-... » read more

Chiplet Interfaces Embrace Failures
By Anne Meixner - 12 Aug, 2025 - Comments: 0

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen. For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-f... » read more

SLM: Actionable Silicon Insights Through Intelligent Measurement and Analysis
By Synopsys - 12 Aug, 2025 - Comments: 0

Developing semiconductors has always been a complex process, with advancements in electronic design automation (EDA) tools and fabrication technologies working to meet growing demands for larger designs, improved power efficiency, and better performance. As chip and system complexity increases alongside higher expectations for product reliability and longevity, traditional methods are reaching ... » read more

Security Verification In Semiconductor Development
By Shylaja Sen - 07 Aug, 2025 - Comments: 0

By Shylaja Sen and Mouadh Ayache As advanced chips become increasingly embedded in our daily lives, developers must remain vigilant about potential security vulnerabilities. On top of PPA (power, performance and area), the focus in semiconductor development has been on minimizing faults to reduce the possibility of failure in mission mode. No one wants an alpha particle to cause their autono... » read more

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