Cloud 2.0


Corporate data centers are reluctant adopters of new technology. There is too much at stake to make quick changes, which accounts for a number of failed semiconductor startups over the past decade with better ideas for more efficient processors, not to mention rapid consolidation in other areas. But as the amount of data increases, and the cost of processing that data decreases at a slower rate... » read more

Tale Of Two HLS Viewpoints


The Design Automation Conference attracts several co-located conferences, symposiums and other such gathering of people, often on more specialized topics than would appeal to the general DAC attendees. Some of them are more research-focused, but one conference is somewhat strange in that it is about a subject that has transitioned to commercial tool development and yet still remains an active a... » read more

IP Integration Challenges Increase


Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

Blog Review: July 8


In this week's picks for his top five technology articles, Ansys' Justin Nescott rolls in with two ways for cyclists to improve safety, the development of the wheelchair and the advancement of fingerprint scanners for healthcare and security. With the launch of the BBC Micro:bit, one part of a program to inspire young people to get into coding and digital creation, ARM's Gary Atkinson shows ... » read more

How Much Security Is Enough?


Semiconductor Engineering sat down to discuss the current state of [getkc id="223" kc_name="security"] and what must be done in the future, with Denis Noël, head of cyber security solutions at [getentity id="22499" e_name="NXP"]; Serge Leef, vice president of new ventures at [getentity id="22017" e_name="Mentor Graphics"]; Andreas Kuehlman, senior vice president and general manager of the soft... » read more

UVM: What’s Stopping You?


These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

The Week In Review: Design/IoT


Synopsys continued its expansion into security with the acquisition of security IP provider Elliptic Technologies. The Canadian company's focus was cryptography cores, security protocol accelerators and processors, Root of Trust embedded security IP modules, secure boot and cryptography middleware as well as content protection IP for integration into SoCs. NXP and Freescale shareholders appr... » read more

Blog Review: July 1


On the eve of his retirement, Cadence's Richard Goering takes a look back at 30 years of covering EDA: the highlights, the lowlights, and the headlights shining into the future. Established nodes are experiencing a much higher demand than one might normally expect at this point in their lifecycle. Mentor's Michael White examines the dynamics and market forces behind the longevity, and the ch... » read more

The Week In Review: Design/IoT


IP Sonics released the latest version of the company's flagship NoC, which expands on their interleaved multi-channel technology and includes new layout optimization features for design flows based on modern physical synthesis and place & route tools. Synopsys extended its PCI Express 4.0 IP to support RAS features to help designers ensure data integrity and increase data protection i... » read more

More Data, Different Approaches


Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

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