Synopsys continues security acquisitions; NXP-Freescale shareholders approve merger; Intel management changes.
Synopsys continued its expansion into security with the acquisition of security IP provider Elliptic Technologies. The Canadian company’s focus was cryptography cores, security protocol accelerators and processors, Root of Trust embedded security IP modules, secure boot and cryptography middleware as well as content protection IP for integration into SoCs.
NXP and Freescale shareholders approved the pending merger, clearing the way for one of the biggest deals of the year.
Intel announced some leadership and organizational changes. President Renee James and Arvind Sodhani, president of Intel Capital, both will step down in January. James will take on an external CEO role.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
SoC bandwidth, integration expand as data centers use more FPGAs for machine learning.
Problems won’t derail next-gen litho, but could limit use and affect schedules.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
What happens when companies are combined? The outcome often isn’t as good as the announcement.
As complexity and device sizes rise, so does the need for an on-chip network.
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.
IP reuse has reduced the urgency for a higher level of abstraction in complex system-level design, but that still could change.
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