Chip Industry Week in Review


Geopolitics Taiwan and the U.S. signed a trade agreement this week, with TSMC and other Taiwanese companies collectively pledging to directly invest at least $250B in investments in advanced semiconductor, energy and AI production and capacity in the U.S.  The agreement also included Taiwan providing another $250B in credit guarantees for additional IC supply chain expansions in the U.S., cap... » read more

Chip Industry Week in Review


SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

Annual Global IC Fabs And Facilities Report


Semiconductor companies announced a significant number of facilities in 2025 as global onshoring efforts continued across manufacturing, materials, packaging, design, and R&D. Investments came from both industry and government sources. Organizations worked together to solve current technology challenges, including soaring demand for AI chips and advanced memory, as well as complex applic... » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)


A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

Scalable AI/ML Method For Improved MTJ Performance (UT Austin, TSMC, TDK Headway)


A new technical paper titled "LEAD: Literature Enhanced Ab Initio Discovery of Nitride Dusting Layers for Enhanced Tunnel Magnetoresistance and Lower Resistance Magnetic Tunnel Junctions" was published by researchers at University of Texas at Austin, TSMC, and TDK Headway Technologies Inc. Abstract "Magnetic tunnel junctions (MTJs) using magnesium oxide (MgO) tunnel barriers face challenges... » read more

Chip Industry Week In Review


Space Forge autonomously generated plasma aboard its ForgeStar-1 satellite, utilizing extreme low Earth orbit (LEO) conditions needed for gas-phase crystal growth of wide- and ultra-wide bandgap materials, GaN, SiC, aluminum nitride, and diamonds. Copper prices surged to a historic record of $12,600 per metric ton, an increase of more than 40% YOY, which will impact the cost of data center b... » read more

Chip Industry Week In Review


Deals: NVIDIA inked a $20B non-exclusive licensing deal with Groq for its inference technology. The startup's founder, Jonathan Ross, and some other employees will join NVIDIA to assist in scaling and advancing the technology. The non-exclusive licensing deal, versus an outright purchase, is a tool other companies have used to avoid antitrust regulation. Samsung Ventures made a strategic inv... » read more

Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

Research Bits: Dec. 16


Back-end integration Researchers from Massachusetts Institute of Technology (MIT) and the University of Waterloo propose a back-end integration platform that enables the fabrication of transistors and memory devices in a single compact stack on a chip. The approach uses amorphous indium oxide as the active channel layer of the back-end transistor. The properties of indium oxide allow a thin... » read more

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