Week In Review: Manufacturing, Test


Packaging and test Intel has invested an additional $475 million in its chip assembly and test manufacturing facility in the Saigon Hi-Tech Park (SHTP) in Vietnam. This takes Intel’s total investment in the Vietnam facility to $1.5 billion. The site assembles and tests Intel’s 5G products and processors. TSMC recently announced a huge increase in capital spending for 2021. A large perce... » read more

Week In Review: Design, Low Power


The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive/Mobility Chip makers in Taiwan will “do their best” to “squeeze out more chips” said Taiwan’s Minister of Economic Affairs Wang Mei-hua after having lunch with representatives of TSMC, UMC, Vanguard International Semiconductor Corp, and Powerchip Semiconductor Manufacturing Co., according to the Taipei Times. After the auto industry initially cut automotive chip orders bec... » read more

New Transistor Structures At 3nm/2nm


Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Week In Review: Manufacturing, Test


Chipmakers Intel posted its quarterly results. But the big question is whether the chip giant will outsource more of its production to the foundries. As reported, Intel has fallen behind TSMC and Samsung in process technology. And Intel may need to outsource some of its chip production to stay ahead. All of this rests on Pat Gelsinger, the new CEO at Intel. Gelsinger will be taking over for... » read more

Week In Review: Design, Low Power


Cadence will acquire NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. “Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, board... » read more

Fearless Chip Forecasts For 2021


It’s been a roller coaster ride in the semiconductor industry. In early 2020, the semiconductor business looked bright, but then the Covid-19 pandemic struck, causing a sudden downturn. By mid-2020, though, the market bounced back, as the stay-at-home economy drove demand for computers, tablets and TVs. The chip market ended on a high note in 2020, but the question is, what’s in store fo... » read more

Week In Review: Manufacturing, Test


Chipmakers and OEMs Intel has appointed Pat Gelsinger as its new chief executive, effective Feb. 15. Gelsinger will also join Intel’s board upon assuming the role. He will succeed Bob Swan, who will remain CEO until Feb. 15. Most recently, Gelsinger served as the CEO of VMware since 2012. He also spent 30 years at Intel, becoming the company’s first chief technology officer. The move fo... » read more

Week In Review: Design, Low Power


Qualcomm will acquire data center chip startup Nuvia for approximately $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia's technology would be incorpora... » read more

Die-To-Die Stress Becomes A Major Issue


Stress is becoming more critical to identify and plan for at advanced nodes and in advanced packages, where a simple mismatch can impact performance, power, and the reliability of a device throughout its projected lifetime. In the past, the chip, package, and board in a system generally were designed separately and connected through interfaces from the die to the package, and from the packag... » read more

← Older posts Newer posts →