Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)


An new technical paper titled "Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond" was published by researchers at TSMC. Abstract "In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitt... » read more

Chip Industry Week in Review


The U.S. government announced new import tariff actions and deals this week, including: The EU: 15% tariff on most goods including semiconductors. According to the EU's president, the action excludes semiconductor equipment. Copper: 50% tariff on all imports of semi-finished copper products and intensive copper derivative products, effective Aug. 1, but raw input material is excluded. ... » read more

The Rise Of Panel-Level Packaging


An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum reticle size in the next few years. These assemblies are best developed using fan-out panel-level packaging, replacing today’s wafer carrier with a panel. Fan-out packaging enables substantially... » read more

Chip Industry Technical Paper Roundup: July 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=456 /] Find more semiconductor research papers here.   » read more

Chip Industry Week in Review


The U.S. government will grant licenses to NVIDIA and AMD to again sell some AI chips — NVIDIA's H20 GPU and AMD's MI308 — to Chinese companies. TrendForce projects that the availability of NVIDIA chips, in particular, will create a surge in demand from Chinese AI firms and cloud service providers, and boost high-bandwidth memory (HBM) consumption. The move could raise China’s share of... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

Chip Industry Week In Review


GlobalFoundries plans to acquire MIPS, adding RISC-V processor IP and PPA optimization software capabilities to its foundry offerings. MIPS will continue to operate as a standalone business within GF. The deal is expected to close in the second half of 2025. The EU rolled out new general-purpose AI rules this week to limit copyright infringement, protect public safety, and require transparency... » read more

Chip Industry Week in Review


[Editor's Note: Early edition due to the U.S. July 4th holiday.] The U.S. government lifted export restrictions that barred Synopsys, Siemens EDA, and Cadence from selling EDA tools to China. In a statement, Synopsys said it received a letter from the U.S. Commerce Department immediately rescinding those restrictions. Siemens issued a similar statement. Which tools or hardware accelerated t... » read more

Novel Assembly Approaches For 3D Device Stacks


The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

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