tag: verification

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Improving LP Verification Efficiency
By Ann Mutschler - 08 May, 2014 - Comments: 1

The addition of low power circuitry can create so many corner cases that many can escape even the best-written testbenches. This has driven the need for so many additional verification cycles to be run that there must be many datacenter managers at semiconductor companies wondering if it is a trick by the power companies to cause an equal amount of power to be consumed by low-power verification... » read more

Can HLS Be Trusted?
By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Formal Verification Of Power-Aware Designs Using JasperGold Low Power Verification App
By Various Writers - 07 May, 2014 - Comments: 1

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, th... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

How To Improve Debug Productivity
By Ann Mutschler - 24 Apr, 2014 - Comments: 0

In the realm of SoC verification world, it often takes a very short amount of time to write the testbench and the code, and the rest of the time — up to 90% — is spent debugging. After all, verification is essentially finding the bugs in a design. Debugging essentially has evolved over the years on the same path and complexity curve as design. Now debugging needs to evolve to keep pace, ... » read more

Extending UVM To Analog
By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Rethinking SoC Verification
By Various Writers - 23 Apr, 2014 - Comments: 1

The introduction of the iPhone in 2007 represented a fundamental shift in electronic system design: moving advanced processing power off of the desktop and into the hands of users everywhere, always. This shift has led to a revolution in mobile—the expansion into the Internet-of-Things, with wearables, connected automobiles and homes. This revolution is causing profound technology challeng... » read more

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