Localized, System-Level Protocol Checks And Coverage Closure


Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Blog Review: April 23


Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

Mask Hotspots Are Escaping The Mask Shop


Although the overwhelming majority of wafer production issues at the 28nm-and- below process nodes are lithography- and OPC-related, the semiconductor industry is starting to see problems caused by mask hotspots: wafer-level production issues that are caused when the shapes specified by optical proximity correction (OPC) are not faithfully reproduced on the mask. Mask hotspots will account for ... » read more

Blog Review: April 16


Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Power Delivery Network Verification Coverage


This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To view this white paper, click here. » read more

High Level Synthesis: Significant Differences Remain


In part 1 of this experts series on high-level synthesis (HLS), Semiconductor Engineering sat down with Mike Meredith, vice president of technical marketing at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. The initial part of the discussion looke... » read more

The Week In Review: Design


Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Blog Review: April 2


Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Big Shift In SoC Verification


Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Get Ready For DVCon Europe


By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

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