tag: ARM

Armv8.5-A Memory Tagging Extension
By Arm - 09 Oct, 2019 - Comments: 0

The Internet worm of 1988 took offline one tenth of the fledgling network, and severely slowed down the remainder [1]. Over 30 years later, two of the most important classes of security vulnerability in code written in C-like languages are still violations of memory safety. According to a 2019 BlueHat presentation, 70% of all security issues addressed in Microsoft products are caused by violati... » read more

More Data, More Processing, More Chips
By Ed Sperling - 07 Oct, 2019 - Comments: 0

Simon Segars, CEO of Arm, sat down with Semiconductor Engineering to talk about the impact of heterogeneous computing and new packaging approaches on IP, the need for more security, and how 5G and the edge will impact compute architectures and the chip industry. SE: There are a whole bunch of new markets opening up. How does Arm plan to tackle those? Segars: Luckily for us, we can design ... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

New Security Risks Create Need For Stealthy Chips
By Ed Sperling - 03 Oct, 2019 - Comments: 0

Semiconductors are becoming more vulnerable to attacks at each new process node due to thinner materials used to make these devices, as well as advances in equipment used to simulate how those chips behave. Thinner chips are now emitting light, electromagnetic radiation and various other types of noise, which can be observed using infrared and acoustic sensors. In addition, more powerful too... » read more

ML, Edge Drive IP To Outperform Broader Chip Market
By Kevin Fogarty - 03 Oct, 2019 - Comments: 0

The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

Blog Review: Oct. 2
By Jesse Allen - 02 Oct, 2019 - Comments: 0

In a video, Cadence's Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. Synopsys' Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards. Mentor's Colin Walls demystifies memo... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Sep, 2019 - Comments: 0

Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Week in Review – IoT, Security, Autos
By Jeff Dorsch - 27 Sep, 2019 - Comments: 0

Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

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