tag: ARM

The Interconnect Game
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Having a single bus protocol is something most SoC engineers can only dream about. Reality is often a jumble of protocols determined by the IP they use, which can slow down a design’s progress. The problem stems largely from re-use and legacy IP. While it might be convenient to use only on an AXI standard protocol from ARM, most chips are a combination of IP tied to specif... » read more

Server Processor War Heats Up
By Kurt Shuler - 26 Apr, 2012 - Comments: 0

By Kurt Shuler Yesterday’s announcement that Intel will acquire Cray’s interconnect hardware program, including IP and 74 employees, is the latest salvo in the race to develop commercially viable massively multicore server processors. On the surface, this acquisition seems like another instance of Intel beefing up its board-level interconnect technology, after having already acquired Fu... » read more

Picking The Right Processor
By Frank Schirrmeister - 24 Apr, 2012 - Comments: 1

By Frank Schirrmeister In an embedded system, the sole connection point between the software and the hardware is the processor. Somewhere right now the effort to develop software for a complex System-on-Chip (SoC) is surpassing the effort of developing the chip itself. As I pointed out in my recent description of the Design West conference in San Jose, complex ecosystems of related content, to... » read more

ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)
By Various Writers - 24 Apr, 2012 - Comments: 0

ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres  about the move to 28nm FD-SOI for smartphones and tablet SOCs.  Take-away message:  FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here's what he said. ~~ [caption id="attachment_441" align="alignleft" wi... » read more

Enterprise Power
By Ed Sperling - 30 Mar, 2012 - Comments: 0

The corporate data center is getting a lot of attention these days. ARM is fighting for a place inside server racks. Cadence has rolled out IP for faster storage standards. And Mentor Graphics has just introduced middleware for embedded Linux. Why? Because unlike the mobile space, where you need billions of units to make margins, in the corporate enterprise you only need millions. Those extr... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

Experts At The Table: IP
By Ed Sperling - 23 Mar, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: The su... » read more

Making Sense Of Virtualization
By Achim Nohl - 22 Mar, 2012 - Comments: 0

By Achim Nohl In the last month I’ve had the opportunity to get some hands-on experience with hardware virtualization and hypervisors. My knowledge so far on this has been mainly limited to what I could read about it and what other people are saying about it. However, the PowerPoint slides I’ve seen leave a lot of white fog between the bullet items. This didn’t make me feel very comfo... » read more

Managing Complexity With Advanced Packaging
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

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