tag: ARM

Corners Up, Margins Down
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

IP Integration Creates Challenges For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse. For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from m... » read more

A Shock To The System
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

Making IP Tradeoffs For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs. Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to a... » read more

IP’s Ecosystem Race
By Ann Mutschler - 22 Apr, 2010 - Comments: 0

By Ann Steffora Mutschler As the semiconductor industry moves from older manufacturing nodes to newer ones what users want from IP providers is changing. So is the way IP providers are answering those needs. Mirroring the broader semiconductor industry’s recognition that it’s simply too expensive, too difficult and too time consuming to do everything alone—the very basis of the IP sec... » read more

Integrated IP Goes Vertical
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 19 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, corporate applications engineer at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Prapanna Tiwari: Traditional techniques like clock-gating an... » read more

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 11 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, ... » read more

The Bright—And Much Larger—Future
By Ed Sperling - 01 Mar, 2010 - Comments: 0

The recent pushes by both Synopsys and Mentor into new markets should say something about the state of EDA. Being able to lay out the wires and subsystems on a chip, not to mention verifying that it all works, will always be vital to getting SoCs to tapeout. But that kind of work will not generate the kind of growth the big EDA companies are looking for—at least not without some major tweaks ... » read more

Smart-Grid Designs Solve Low-Power Riddles
By Various Writers - 11 Feb, 2010 - Comments: 0

By Ellen Konieczny Imagine that you go to your kitchen to get a drink and pass your home’s energy-usage monitor. Due to a recent heat wave, you see that your energy usage is already at what it usually is for the entire month. Yet you’ve still got one week left in your billing cycle. To keep the bill low, you turn your A/C thermostat up a degree and make a mental note to not keep lights o... » read more

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