tag: ARM

Remaking The Design Landscape
By Ed Sperling - 28 Jan, 2010 - Comments: 0

By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Low-Power Architectures Go Mainstream
By Pallab Chatterjee - 14 Jan, 2010 - Comments: 0

By Pallab Chatterjee Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology. There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions fr... » read more

Differentiating Embedded Processors
By Ed Sperling - 10 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler The embedded processor world addresses a vast range of applications – from the datacenter to the biomedical device – all of which have critical power needs that vary with the use. Power concerns continue to dominate the embedded system whether it is avoid a noisy fan in a TV set-top box, allow video on a mobile phone or minimize pricey cooling costs in the datac... » read more

Methodology Shifts Ahead
By Pallab Chatterjee - 19 Nov, 2009 - Comments: 0

By Pallab Chatterjee The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design. Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushe... » read more

Power Delivery Issues
By Ed Sperling - 10 Nov, 2009 - Comments: 0

By Ed Sperling Reducing the voltage in a system on chip is like turning down the water pressure on a home plumbing system. Pretty soon you find out that not all the faucets work properly because there isn’t enough pressure behind them. While it’s vital to drop the voltage to boost battery life in mobile devices, not to mention reduce the overall power consumption in plug-in devices, t... » read more

Making Connections
By Ed Sperling - 28 Oct, 2009 - Comments: 0

By Ed Sperling The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living. The numbe... » read more

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

When It Comes To Intellectual Property, Size Matters
By Various Writers - 19 Aug, 2009 - Comments: 0

By Geoffrey James Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model. “As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith. The IP segment, however, hasn�... » read more

Dropping The Voltage: Now What?
By Ed Sperling - 16 Aug, 2009 - Comments: 0

By Ed Sperling Ratcheting down the voltage in an SoC design seems like the simplest way to reduce power consumption, but it doesn’t always work out that way. In fact, reducing voltage can have some rather strange and unexpected effects at all levels of chip design, including testing and debugging. The problem is that not all parts of the chip work the same way without a minimum am... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

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