Pre-Silicon Verification and Validation Methodology Targeting Robust RISC-V Chip Designs (BSC)


A new technical paper, "Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL," was published by researchers at Barcelona Supercomputing Center. Abstract "The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a ho... » read more

Chip Industry Week In Review


Geopolitics U.S. lawmakers are urging tighter export controls on advanced semiconductor manufacturing equipment (SME) to China, warning existing loopholes threaten national security. "China is working to build domestic SME by exploiting access to U.S. and allied subcomponents required to produce tools," states the letter, which also says better coordination with allies is essential. The U.S.... » read more