tag: Breker Verification Systems

Week In Review: Design, Low Power
By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Making Autonomous Vehicles Safer
By Kevin Fogarty - 10 Jan, 2019 - Comments: 2

While self-driving vehicles are beta-tested on some public roads in real traffic situations, the semiconductor and automotive industries are still getting a grip on how to test and verify that vehicle electronics systems work as expected. Testing can be high stakes, especially when done in public. Some of the predictions about how humans will interact with autonomous vehicles (AVs) on public... » read more

AV Testing Advances Without Standards
By Kevin Fogarty - 08 Jan, 2019 - Comments: 0

The failure of the AV START Act in the United States Senate did more than just delay U.S. federal regulations for self-driving car technology that has yet to progress beyond the pilot-test stage. It delayed discussions that could have narrowed the almost infinite number of choices automated vehicles (AVs) must be prepared to make by creating guidelines defining what constitutes "safe" operat... » read more

Fundamental Shifts In 2018
By Brian Bailey - 20 Dec, 2018 - Comments: 1

What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

What Makes A Chip Design Successful Today?
By Brian Bailey - 13 Dec, 2018 - Comments: 0

"Transistors are free" was the rallying cry of the semiconductor industry during the 1990s and early 2000s. That is no longer true. The end of Dennard scaling made the simultaneous use of all the transistors troublesome, but transistors remained effectively unlimited. This led to an era where large amounts of flexibility could be built into a chip. It didn't matter if all of it was being use... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

Overcoming Gender Stereotypes In Tech
By Ann Mutschler - 23 Nov, 2018 - Comments: 5

Gender inequality in the workplace is more complex and deep-rooted than most studies have shown, and efforts to address those issues are only scratching the surface. The problem runs deeper than just moving women into upper management. It extends all the way through organizations in ways that aren't always obvious. “I've been talking to senior women in engineering and junior women in en... » read more

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