tag: cache

Power/Performance Bits: July 18
By Jesse Allen - 18 Jul, 2017 - Comments: 0

Ad hoc "cache hierarchies" Researchers at MIT and Carnegie Mellon University designed a system that reallocates cache access on the fly, to create new "cache hierarchies" tailored to the needs of particular programs. Dubbed Jenga, the system distinguishes between the physical locations of the separate memory banks that make up the shared cache. For each core, Jenga knows how long it would t... » read more

System Performance Analysis At ARM
By Arm - 07 Dec, 2016 - Comments: 0

Performance analysis is a vital task in modern SoC design. An under-designed SoC may run too slowly to keep up with the demands of the system. An over-designed SoC will consume too much power and require more expensive IP blocks. At ARM we want to help our partners build SoCs that deliver the best performance within their power and area budgets. The simple truth is that this is more difficul... » read more

Rethinking Main Memory
By Hunglin Hsu - 10 May, 2016 - Comments: 3

With newer, bigger programs and more apps multitasking simultaneously, the answer to making any system run faster, from handheld to super computer, was always just to add more DRAM. . . and more, and more and more. From data centers to wearables, that model no longer works. By offloading the storage of programs to less expensive solid-state drives (SSDs) and only using a small amount of exp... » read more

Heterogeneous Multi-Core Headaches
By Ed Sperling - 28 Jan, 2016 - Comments: 4

Cache coherency is becoming more pervasive—and more problematic—as the number of heterogeneous cores used in designs continues to rise. Cache coherency is an extension of caching, which has been around since the 1970s. The notion of a cache has a long history of being utilized to speed up a computer's main memory without adding expensive new components. Cache coherency's introduction coi... » read more

3 Big Bottlenecks For Design
By Ed Sperling - 09 Oct, 2014 - Comments: 0

Throughout the history of design for ICs, systems and software, bottlenecks emerge as one part of the design evolves more slowly than the next. It's frequently due to the fact that difficult engineering issues haven't been solved yet in one part of the design. Sometimes they can't be solved in a reasonable amount of time or for a reasonable amount of money and something else has to take its pla... » read more

HotChips: Power8
By Barry Pangrle - 12 Sep, 2013 - Comments: 2

It’s another year, another HotChips Conference and another update on IBM’s POWER processor. IBM continues to impress with its big iron processor, and this year it’s the new POWER8. IBM announced more details of its new POWER8 processor at HotChips and IBM now joins Intel at 22nm, but with the twist that IBM’s process is based on SOI technology. The POWER8 quadruples the thread count ... » read more

Will Wide I/O Reduce Cache?
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

Hot Chips 2009: It’s All About Multicore And Low-Power
By Pallab Chatterjee - 27 Aug, 2009 - Comments: 0

By Pallab Chatterjee The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities ... » read more

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