tag: Cadence Design Systems

5G Communications
By Cadence - 04 Aug, 2021 - Comments: 0

This white paper examines the recent advances that the modeling, simulation, and design automation capabilities in Cadence® AWR® software are helping designers develop the antenna and RF front-end components that are making 5G a reality. This primer offers a breadth of application notes on the innovative wizards and synthesis technologies that enable engineers designing 5G communications syst... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 30 Jul, 2021 - Comments: 0

Automotive SGS-TÜV Saar certified that Cadence’s Tensilica Xtensa processors with FlexLock meets the ISO 26262:2018 standard to ASIL-D level. The new FlexLock feature is key to the certification because it supports lockstep, a fault-tolerant method that runs the same operation on two cores at the same time and then compares the output. Any difference in the output can be examined for issues... » read more

Sweeping Changes Ahead For Systems Design
By Ann Mutschler - 29 Jul, 2021 - Comments: 0

Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

RF To Millimeter-Wave Front-End Component Design Trends For 5G Communications
By Cadence - 28 Jul, 2021 - Comments: 0

This white paper discusses design challenges and solutions related to the "third wave" of communications, presenting several case studies in which the Cadence AWR Design Environment platform has been used to develop products for 5G and beyond. Examples include a multiband active antenna tuner for cellular internet of things (IoT) machine-type communications (mMTC) applications, a linear power a... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 23 Jul, 2021 - Comments: 0

Security Xilinx is investing an undisclosed amount in fabless semiconductor startup Kameleon Security, which is working on a cyber protection chip for servers, data centers, and cloud computing. The proactive Security Processing Unit (ProSPU) already secures the boot and has a root of trust (RoT). The chip will be demonstrated at the Open Compute Project (OCP) Global Summit, which is planned f... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 16 Jul, 2021 - Comments: 0

Chipmakers The chip industry is buzzing over a Wall Street Journal report that Intel is in talks to buy GlobalFoundries (GF) for $30 billion. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel planned to jumpstart its foundry business within its own fabs. But it... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 16 Jul, 2021 - Comments: 0

Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Massive IoT Interop Fuels Protocol Battle
By Bryon Moyer - 15 Jul, 2021 - Comments: 0

Wireless standards are plentiful, but most are not capable of being scaled to the level of a smart city. As a result, such networks have been built application-by-application using proprietary stacks, often with non-interoperable network layers. That, in turn, has slowed the proliferation of dense wireless connectivity at scale. “In a hyper-connected world, connectivity choices are driv... » read more

Chipmakers Getting Serious About Integrated Photonics
By Brian Bailey - 12 Jul, 2021 - Comments: 3

Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Reducing Power Delivery Overhead
By Brian Bailey - 08 Jul, 2021 - Comments: 0

The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

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