tag: Cadence

Securing Offload Engines For A Robust Secure SoC System
By Sriram Sharma Kalluri - 01 Jul, 2021 - Comments: 0

Welcome to the Securing Offload Engines blog series where we will explore different approaches to security implementations and look at system examples involving Cadence Tensilica Xtensa Processors. In this blog, we will look at why it is important to build a robust secure SoC and introduce some of the common approaches to securing the offload engines. In subsequent posts, we will look at each o... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2021 - Comments: 0

Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

Internet of Things (IoT)
By Cadence - 30 Jun, 2021 - Comments: 0

The wide range of internet of things (IoT) applications in development today are made possible by smart devices operating across different network configurations, frequencies, power requirements, and protocols. Developing cost-effective IoT solutions requires a smart, organized approach to radio and antenna integration within a design flow that may have little to do with traditional RF product ... » read more

Data Centers On Wheels
By Ann Mutschler - 28 Jun, 2021 - Comments: 2

Automotive architectures are evolving quickly from domain-based to zonal, leveraging the same kind of high-performance computing now found in data centers to make split-second decisions on the road. This is the third major shift in automotive architectures in the past five years, and it's one that centralizes processing using 7nm and 5nm technology, specialized accelerators, high-speed memor... » read more

Week In Review: Design, Low Power
By Jesse Allen - 25 Jun, 2021 - Comments: 0

Synopsys will acquire the semiconductor and flat panel display solutions of BISTel. The acquisition will add an integrated and comprehensive yield management and prediction solution for manufacturing quality and efficiency. BISTel provides engineering equipment systems and AI applications for smart manufacturing in a range of industries. "Combining Synopsys' and BISTel's expertise in fab soluti... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 25 Jun, 2021 - Comments: 0

Automotive Cadence will be capturing design insights from Presto Engineering, an ASIC designer working on high-performance system-in-package (SiP) development for the automotive and Industrial IoT markets. Presto, which also provides semiconductor services such as test and qualification, will use Cadence’s EDA and analysis tools (Allegro X Package Designer Plus, Clarity 3D Solver, Sigrity Xt... » read more

Rocky Road To Designing Chips In The Cloud
By Ann Mutschler - 24 Jun, 2021 - Comments: 0

EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Smart Home Device Communication In The Era Of Hyperconnectivity
By Frank Schirrmeister - 24 Jun, 2021 - Comments: 0

In our increasingly hyperconnected world, a fascinating area to watch is what I would call "the last 100 feet, give or take." There are many standards like Wi-Fi, Bluetooth, Zigbee, or Thread used for IoT device connectivity. There are very active discussions about how our smart devices should be allowed to talk to other resources, like our neighbor's Wi-Fi. In the IoT's municipal and industria... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Blog Review: June 23
By Jesse Allen - 23 Jun, 2021 - Comments: 0

Synopsys' Manuel Mota shows how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Siemens EDA's Chris Spear explains the relationship between classes and objects in SystemVerilog with a handy visualization and notes the difference between SystemVerilog ... » read more

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