tag: Cadence

OIP Ecosystem Forum 2020
By Paul McLellan - 10 Sep, 2020 - Comments: 0

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosystem around each of the new processes. There were then three keynotes by the leaders of the three big EDA companies. That was followed by more technical ... » read more

Compiling And Optimizing Neural Nets
By Bryon Moyer - 10 Sep, 2020 - Comments: 0

Edge inference engines often run a slimmed-down real-time engine that interprets a neural-network model, invoking kernels as it goes. But higher performance can be achieved by pre-compiling the model and running it directly, with no interpretation — as long as the use case permits it. At compile time, optimizations are possible that wouldn’t be available if interpreting. By quantizing au... » read more

Blog Review: Sept. 9
By Jesse Allen - 09 Sep, 2020 - Comments: 0

Mentor's Jacob Wiltgen considers the recent advances in safety critical engineering and how automated the lifecycle can become, where tools form a set of checks and balances to ensure the accuracy of results. Cadence's Paul McLellan finds out what's new at TSMC, including a new R&D center, fab construction, capacity increases for existing nodes, and what the company sees for beyond its N... » read more

How ML Enables Cadence Digital Tools To Deliver Better PPA
By Cadence - 09 Sep, 2020 - Comments: 0

Artificial intelligence (AI) and machine learning (ML) are emerging as powerful new ways to do old things more efficiently, which is the benchmark that any new and potentially disruptive technology must meet. In chip design, results are measured in many different ways, but common metrics are power (consumed), performance (provided), and area (required), collectively referred to as PPA. These me... » read more

Formal Verification Becoming Critical To Auto Security, Safety
By Ann Mutschler - 09 Sep, 2020 - Comments: 0

Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications. Formal has been essential component of automotive semiconductor verification for some time. Even before the advent of ADAS and semi-autonomous vehicles — and functional safety specifications like ISO 26262 and cybersecur... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Sep, 2020 - Comments: 0

Tools & IP Arm unveiled the Cortex-R82, a 64-bit, Linux-capable Cortex-R processor targeted for next-generation enterprise and computational storage solutions. The Cortex-R82 provides 2x performance depending on workload compared to previous Cortex-R generations and provides access of up to 1TB of DRAM for advanced data processing in storage applications. It offers an optional memory manag... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 04 Sep, 2020 - Comments: 0

AI on edge Cadence’s Tensilica Vision P6 DSP IP will be in Kneron’s KL720, a 1.4TOPS AI system-on-chip (SoC) targeted for AI of things (AIoT), smart home, smart surveillance, security, robotics and industrial control applications. Arm announced its Arm Cortex-R82, a 64-bit, Linux-capable Cortex-R processor for enterprise and computational storage systems. The processor is designed to pr... » read more

Software-Defined Vehicles
By Bryon Moyer - 03 Sep, 2020 - Comments: 1

Automobiles long ago stopped being purely mechanical systems. But as more components are electrified — and, in particular, as the drivetrain is electrified — cars are becoming software-defined vehicles. Some think of such cars as computers on wheels. But as these systems continue to evolve, adding in more assisted and semi-autonomous capabilities, that comparison is looking increasingly ... » read more

Establishing Connectivity Between Die and BGA
By Tyler Lockman - 03 Sep, 2020 - Comments: 0

The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do not use a front-end schematic. Even if you have a schematic, you may find yourself making logic swaps in the layout where the additional context of the r... » read more

Interconnects Emerge As Key Concern For Performance
By Ed Sperling - 03 Sep, 2020 - Comments: 0

Interconnects are becoming increasingly challenging to design, implement and test as the amount of data skyrockets and the ability to move that data through denser arrays of compute elements and memories becomes more difficult. The idea of an interconnect is rather simple, but ask two people what constitutes an interconnect and you're likely to get very different answers. Interconnects are e... » read more

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