tag: Cadence

Week In Review: Design, Low Power
By Jesse Allen - 24 May, 2019 - Comments: 0

M&A Marvell will acquire Avera Semiconductor, the ASIC business of GlobalFoundries, for $650 million in cash at closing plus an additional $90 million in cash if certain business conditions are satisfied within the next 15 months. The agreements include transfer of Avera's revenue base, strategic design wins with infrastructure OEMs, and a new long-term wafer supply agreement between Globa... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

In-Chip Monitoring Becoming Essential Below 10nm
By Ann Mutschler - 20 May, 2019 - Comments: 0

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 May, 2019 - Comments: 0

Tools & IP Cadence introduced the Tensilica Vision Q7 DSP, which provides up to 1.82 TOPS and is specifically optimized for simultaneous localization and mapping (SLAM). The DSP has a very long instruction word (VLIW) SIMD architecture, an enhanced instruction set supporting 8/16/32-bit data types and optional VFPU support for single and half precision, and a number of iDMA enhancements in... » read more

Is ADAS The Edge?
By Ann Mutschler - 16 May, 2019 - Comments: 0

Debate is brewing over whether ADAS applications fall on the edge, or if they are better viewed squarely within the context of the automotive camp. There is more to this discussion than just semantics. The edge represents a huge greenfield opportunity for electronics of all sorts, and companies from the mobile market and from the cloud are both rushing to stake their claim. At this point the... » read more

Incremental System Verification
By Brian Bailey - 16 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2019 - Comments: 0

Cadence's Sean Dart shares an example of the kind of optimizations HLS tools can perform that would be difficult to find and implement by hand-coding RTL. Synopsys' Taylor Armerding takes a look at three cybersecurity initiatives from the U.S. government, from an IoT bill to improved voting machines, and whether they're likely to work. In a video, Mentor's Colin Walls points to why flashi... » read more

Chiplet Momentum Builds, Despite Tradeoffs
By Brian Bailey - 13 May, 2019 - Comments: 0

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 May, 2019 - Comments: 0

Tools & IP Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduct... » read more

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