tag: Cadence

Reducing Latency, Power, and Gate Count with Floating-Point FMA
By Cadence - 12 Dec, 2018 - Comments: 0

Today’s digital signal processing applications such as radar, echo cancellation, and image processing are demanding more dynamic range and computation accuracy. Floating-point arithmetic units offer better precision, higher dynamic range, and shorter development cycles when compared with fixed-point arithmetic units. Minimizing the design’s time to market is more important than ever. Algori... » read more

Blog Review: Dec. 12
By Jesse Allen - 12 Dec, 2018 - Comments: 0

Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

Autonomous Vehicle Design Begins To Change Direction
By Ann Mutschler - 06 Dec, 2018 - Comments: 0

Tools that are commonly used in semiconductor design are starting to be applied at the system level for assisted and autonomous vehicles, setting the stage for more complex simulated scenarios and electronic system design. Simulation is well understood for designing automotive ICs, but now it also is being used to design vehicle architectures and sensors, as well as for sensor miniaturizatio... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

Blog Review: Dec. 5
By Jesse Allen - 05 Dec, 2018 - Comments: 0

Mentor's Harry Foster digs into verification effectiveness in FPGA projects and what it means that so many non-trivial bugs escape into production. Cadence's Paul McLellan checks out an effort to integrate photonics with CMOS and find the tradeoffs in three different approaches, plus the view of photonics as applied to military aircraft. Synopsys' Richard Solomon shares some highlights on... » read more

Making Sure A Heterogeneous Design Will Work
By Ed Sperling - 03 Dec, 2018 - Comments: 0

An explosion of various types of processors and localized memories on a chip or in a package is making it much more difficult to verify and test these devices, and to sign off with confidence. In addition to timing and clock domain crossing issues, which are becoming much more difficult to deal with in complex chips, some of the new devices are including AI, machine learning or deep learning... » read more

Virtual Design Chains At The EDA Forum
By Frank Schirrmeister - 29 Nov, 2018 - Comments: 0

The German edacentrum’s EDA Forum was held in Berlin, Germany, in early November. It was very interesting to see the design chain effects in the automotive domain, very visible in a panel yours truly was part of, together with Audi, Bosch, Infineon, MicroChip, Synopsys, Mentor, and the BMBF. Driven from the top of the design chain, the direction is clearly to go more virtual to optimize the c... » read more

Looking Beyond The CPU
By Brian Bailey - 29 Nov, 2018 - Comments: 0

CPUs no longer deliver the same kind of of performance improvements as in the past, raising questions across the industry about what comes next. The growth in processing power delivered by a single CPU core began stalling out at the beginning of the decade, when power-related issues such as heat and noise forced processor companies to add more cores rather than pushing up the clock frequency... » read more

Bare Metal Programming
By Ann Mutschler - 29 Nov, 2018 - Comments: 0

As the need for safety and security grows across application areas such as automotive, industrial, and in the cloud, the semiconductor industry is searching for the best ways to protect these systems. The big question is whether it is better to build security and safety into hardware, into software, or both. The answer isn't entirely clear yet, but one of the options under consideration is s... » read more

IP Tracking and Management
By Brian Bailey - 29 Nov, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss IP tracking and management with Ranjit Adhikary, VP of marketing for ClioSoft; Jim Bruister, director digital systems (since retired) at Silvaco; Marc Greenberg, product marketing group director at Cadence; and Kelvin Low, VP of Marketing at Arm. What follows are excerpts from that conversation. SE: What is the scope of the problem? What are ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy