tag: Cadence

The Rising Value Of Data
By Ed Sperling - 09 Aug, 2017 - Comments: 0

The volume of data being generated by a spectrum of devices continues to skyrocket. Now the question is what can be done with that data. By Cisco's estimates, traffic on the Internet will be 3.3 zetabytes per year by 2021, up from 1.2 zetabytes in 2016. And if that isn't enough, the flow of data isn't consistent. Traffic on the busiest 60-minute period in a day increased 51% in 2016, compare... » read more

IP Business Changing As Markets Shift
By Ed Sperling - 03 Aug, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IP protection, tracking and reuse with Srinath Anantharaman, CEO of [getentity id="22203" e_name="ClioSoft"]; and Jeff Galloway, CTO of Silicon Creations; Marc Greenberg, group director of product marketing for [getentity id="22032" e_name="Cadence"]'s IP Group; and John Koeter, vice president of marketing for [getentity id="22035" e_name="Synopsys"... » read more

Blog Review: Aug. 2
By Jesse Allen - 02 Aug, 2017 - Comments: 0

In a video, Cadence's Marc Greenberg describes the post-package repair capability in LPDDR4 and why it's important for future LP/DDR5 memories. Synopsys' Kiran Vittal looks at formal, machine learning, and when computers beat humans at games. Mentor's Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects. ARM's Freddi Jeffries digs into why com... » read more

CCIX Enables Machine Learning
By Brian Bailey - 31 Jul, 2017 - Comments: 5

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual hardware on which these run, and that brings us into the even less sexy world of interfaces. One such interface, the Cache Coherent Interconnect for Accelerators (CCIX), pronounced C6, aims to make th... » read more

The Week In Review: Design
By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

Emulating Systems Of Systems
By Frank Schirrmeister - 27 Jul, 2017 - Comments: 0

System design is all the craze these days. I have been in notably more discussions recently about how one can verify systems of systems. Does an airplane or a car lend itself to an array of emulators? Are multiple abstractions needed? How can design teams span electrical, mechanical, and thermal—as well as analog and digital—effects? Do companies need to re-organize to deal with system desi... » read more

How Much Verification Is Necessary?
By Ann Mutschler - 27 Jul, 2017 - Comments: 0

Since the advent of IC design flows, starting with RTL descriptions in languages like Verilog or VHDL, project teams have struggled with how much verification can and should be performed by the original RTL developers. Constrained-random methods based on high-level languages such as [gettech id="31021" t_name="e"] or [gettech id="31023" comment="SystemVerilog"] further cemented the role of t... » read more

Blog Review: July 26
By Jesse Allen - 26 Jul, 2017 - Comments: 1

Mentor's Dan Driscoll digs into designing for safety and security on the Xilinx UltraScale+ MPSoC and the different mechanisms that support subsystem isolation. Cadence's Paul McLellan listens in on a talk by Bosch's Volkmar Denner on the future of communications and AI in connected autos. Synopsys' Robert Vamosi points to a recently-discovered vulnerability that could be present in thous... » read more

The Week In Review: Design
By Jesse Allen - 21 Jul, 2017 - Comments: 0

Tools Mentor released the latest version of its FloTHERM CFD software for electronics cooling simulation, adding a new design window to create and solve variants of a model with features to improve scenario definition and design space exploration. Other enhancements include support for Phase Change Materials, more abilities for PCB designs, and an improved parallel solver. Markets IC Insig... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

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