tag: Cadence

The Week In Review: Design
By Jesse Allen - 19 May, 2017 - Comments: 0

M&A Consultancy Sondrel acquired IMGworks, formerly the design services unit of Imagination. Sondrel says it plans to focus on design services for ADAS systems, AI, and machine vision and learning devices. Terms of the deal were not disclosed. Tools Cadence expanded its formal verification platform, JasperGold, adding linting and clock domain crossing apps that address RTL signoff ... » read more

Maintaining Power Profiles At 10/7nm
By Ann Mutschler - 17 May, 2017 - Comments: 0

Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Blog Review: May 17
By Jesse Allen - 17 May, 2017 - Comments: 0

Synopsys' Robert Vamosi digs into last Friday's massive ransomware infection that impacted the UK health system, a Spanish telecom, and many other organizations running unpatched Windows – and whether there's a second version out there. Cadence's Paul McLellan reports on the latest developments and future of FD-SOI from the SOI Silicon Valley Symposium. Mentor's Joe Hupcey III chats wit... » read more

Whatever Happened to High-Level Synthesis?
By Brian Bailey - 16 May, 2017 - Comments: 0

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Moore’s Law: Toward SW-Defined Hardware
By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 12 May, 2017 - Comments: 0

Market research Intel held a slim 4% lead over Samsung for the number one position in terms of chip sales in the first quarter, according to IC Insights. But as reported, Samsung is on pace to displace Intel as the world’s largest semiconductor supplier in the second quarter, according to the firm. Meanwhile, in the ranking, SK Hynix and Micron made the biggest moves. And there was one new e... » read more

The Efficiency Problem
By Samer Hijazi - 11 May, 2017 - Comments: 0

Part one of this report addressed the efficiency problem in neural networks. This segment addresses efficiencies in training, quantization, and optimizing the network and the hardware. Minimize the Bits (CNN Advanced Quantization) Training a CNN involves assigning weight vectors to certain results, and applying adaptive filters to those results to determine the positives, false positives, a... » read more

Power Challenges At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 1

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

High-Level Low-Power System Design Optimization
By Cadence - 10 May, 2017 - Comments: 0

High-level decisions have the most impact on power consumption, but the effect of those decisions cannot be known until the hardware is implemented. This paper walks the reader through an industrial high-level low-power design methodology that enables the designer to consider and quantitatively evaluate a broad range of hardware implementations to find the most power-efficient architecture. Thi... » read more

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