tag: Cadence

The Week In Review: Design
By Jesse Allen - 28 Oct, 2016 - Comments: 0

IP ARM unveiled a suite of products focused on the IoT, with new processors, radio technology, subsystems, end-to-end security and a cloud-based services platform. Included are Cortex-M23 and Cortex-M33, the first embedded processors based on the ARMv8-M architecture. The Cortex-M33 features configuration options including a coprocessor interface, DSP and floating point computation, while th... » read more

Embedded FPGAs Going Mainstream?
By Brian Bailey - 27 Oct, 2016 - Comments: 0

Systems on chip have been made with many processing variants ranging from general-purpose CPUs to DSPs, GPUs, and custom processors that are highly optimized for certain tasks. When none of these options provide the necessary performance or consumes too much power, custom hardware takes over. But there is one type of processing element that has rarely been used in a major SoC— the [gettech id... » read more

“Eating Your Own Dog Food” When Developing An Emulator
By Frank Schirrmeister - 27 Oct, 2016 - Comments: 0

It’s a great week for emulation week with ARM TechCon happening in Silicon Valley. Palladium Z1 is a finalist for Best Product in the categories “Best Chip” and “Best System” and we started the week with an announcement that Fujitsu adopted the Cadence Palladium Z1 Enterprise Emulation Platform for their ARMv8-based “Post-K Supercomputer Development.” Cadence has faced some of the... » read more

Too Big To Simulate?
By Ann Mutschler - 27 Oct, 2016 - Comments: 2

With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 27 Oct, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Emulation’s Footprint Grows
By Brian Bailey - 27 Oct, 2016 - Comments: 0

It wasn't that many years ago that [getkc id="30" comment="emulation"] was an expensive tool available to only a few, but it has since become indispensable for a growing number of companies. One obvious reason is the growing size of designs and the inability of [getkc id="11" kc_name="simulation"] to keep up. But emulation also has been going through a number of transformations that have made i... » read more

Massively Parallel Electrically Aware Design
By Cadence - 26 Oct, 2016 - Comments: 0

In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server ar... » read more

Blog Review: Oct. 26
By Jesse Allen - 26 Oct, 2016 - Comments: 0

Synopsys' Robert Vamosi provides some additional information on last Friday's massive DDoS attack against DNS provider Dyn, which hampered access to many big-name websites. On the same note, Cadence's Paul McLellan warns of the hazards default and easy-to-guess device passwords present to people far beyond the original user. Mentor's Arvind Narayanan warns that the 10nm era has changed ph... » read more

Gaps In The Verification Flow
By Brian Bailey - 25 Oct, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Closing The Power Integrity Gap
By Ann Mutschler - 19 Oct, 2016 - Comments: 0

Voltage drop has always been a significant challenge. As far back as 130nm, specialist tools were being used to ensure that enough local decoupling capacitance (decap) cells were inserted in addition to larger decaps implemented around the SoC. But advanced nodes are complicating matters and further increasing complexity. These technological challenges, which underlie the power, performance ... » read more

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