tag: Cadence

Models Are Dead? Long Live Models
By Frank Schirrmeister - 28 Jul, 2016 - Comments: 0

During the first half of this year I had more discussions with customers on models again. Are models back? For what purpose? In short, it looks like models are well adopted and in use for software development. For performance and architecture analysis, however, as a recent presentation from Renesas at CDNLive Japan shows, users just use RTL as that accuracy is required. In combination with emul... » read more

New Drivers For Test
By Brian Bailey - 28 Jul, 2016 - Comments: 0

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Speeding Up The Design Process
By Ed Sperling - 28 Jul, 2016 - Comments: 0

A rush to plant a stake in new markets, coupled with uncertainty about how to generate a reasonable return on investment in those markets, is ratcheting up pressure on chipmakers. They now must come up with more customized solutions in less time, frequently in smaller volumes, and with the ability to modify them in shorter time spans if market opportunities shift in unexpected ways. This aff... » read more

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Automating Inter-Layer In-Design Checks In Rigid-Flex PCBs
By Cadence - 27 Jul, 2016 - Comments: 0

Flexible PCBs (flex/rigid-flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. As flexible PCB fabrication technology has matured in response to demands for smaller, lighter products, new design challenges have emerged. This paper discusses some of the key challenges to address and also ... » read more

Blog Review: July 27
By Jesse Allen - 27 Jul, 2016 - Comments: 0

Mentor's Tom Fitzpatrick investigates how to add new behavior to an existing testbench with the UVM factory class. Synopsys' Srinivas Vijayaragavan and Pooja Gupta dig into new features of SAS 24G, including how its effective speed was doubled to 24G though signaling rate remains at 22.5G. Cadence's Paul McLellan highlights a presentation from the SEMI/Gartner Market Symposium focused on ... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 27 Jul, 2016 - Comments: 0

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 26 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

The Week in Review: IoT
By Jeff Dorsch - 22 Jul, 2016 - Comments: 0

Deals The big news of the week, of course, is SoftBank Group’s proposed acquisition of ARM Holdings for a breathtaking $32.2 billion in cash. In announcing the deal, the companies made it abundantly clear that the proposed acquisition is chiefly about Internet of Things technology. “When I think about the investment and the commitment that’s going to be required to develop the future te... » read more

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