tag: Cadence

Blog Review: July 13
By Jesse Allen - 13 Jul, 2016 - Comments: 0

Synopsys' Mansi Chadha looks back at the history of storage and the evolution of SCSI. Cadence's Paul McLellan highlights some of the latest news from the world of neural networks. Mentor's Darrell Teegarden digs into the challenges of modeling fuel cells and walks through how to build one. Ansys' Justin Nescott features a giant, three-instrument music box in his picks for the week's t... » read more

The Week in Review: IoT
By Jeff Dorsch - 08 Jul, 2016 - Comments: 0

Networks The Netherlands and South Korea are both laying claim to installing the first nationwide Internet of Things networks in the world. In the Netherlands, KPN has connected the country with a low-power, wide-area network optimized for IoT. SK Telecom is serving Korea with coast-to-coast IoT coverage, and the Korean carrier plans to spend up to $86.8 million through the end of 2017 on upg... » read more

Grappling With Auto Security
By Ann Mutschler - 07 Jul, 2016 - Comments: 1

It’s a changed world under the hood of automobiles today, as vehicles become increasingly connected to infrastructure and each other. But that connectedness also is creating new security risks. Growing complexity is one piece of the problem. There are upwards of 80 electronic control units (ECUs) and more than 100 million lines of code in an average vehicle. On top of that, there are m... » read more

Verification Engine Disconnects
By Ed Sperling - 06 Jul, 2016 - Comments: 0

Moving verification data seamlessly between emulation, simulation, FPGA prototyping and formal verification engines may be possible on paper, but it is proving more difficult to implement in the real world. [getkc id="10" kc_name="Verification"] still consumes the most time and money in the design process. And while the amount of time spent on verification in complex designs has held relativ... » read more

Blog Review: July 6
By Jesse Allen - 06 Jul, 2016 - Comments: 0

Cadence's Chris Rowen discusses optimizing neural networks for low-energy and high-throughput applications in his latest video. What should you include in an IoT chip? Synopsys' Eric Huang presents the case for building in USB. Mentor's Matthew Hogan takes a look at what's needed for speedy interconnect robustness verification. Rambus' Aharon Etengoff digs into a potential new enterpri... » read more

GPUs Power Ahead
By Ann Mutschler - 05 Jul, 2016 - Comments: 0

GPUs, long a sideshow for CPUs, are suddenly the rising stars of the processor world. They are a first choice in everything from artificial intelligence systems to automotive ADAS applications and deep learning systems powered by [getkc id="261" kc_name="convolutional neural network"]. And they are still the mainstays of high-performance computing, gaming and scientific computation, to name ... » read more

Balancing Emulation And FPGA-Based Prototyping For Software Development
By Frank Schirrmeister - 30 Jun, 2016 - Comments: 0

This year’s Design Automation Conference (DAC) has just finished and confirmed some of the trends I discussed in my last blog, “The Top Five Trends in Verification to Watch For at DAC 2016”, specifically when it comes to the set of connected engines, or “COVE” as Jim Hogan dubbed it. The Cadence Theater at DAC is always a good opportunity to listen to hands-on customer experiences, an... » read more

Uncertainty Rocks Chip Market
By Ed Sperling - 30 Jun, 2016 - Comments: 1

The semiconductor industry is undergoing sweeping changes in every direction, making it far more difficult to figure out which path to take next, when to take it, and how to get there. The next few years will redefine which semiconductor companies emerge as leaders, which ones get pushed down or out or absorbed into other companies, and which markets will be the most lucrative. And that coul... » read more

Electrical-Mechanical Tool Flow Revisited
By Ann Mutschler - 30 Jun, 2016 - Comments: 0

For many years, the design tool industry has entertained the idea of combining both electrical and mechanical design into a single user experience, with a single database as a foundation. Major tool vendors, at least on the electrical side, have taken the matter seriously and confirm that activities towards a single flow have been considered, particularly as the [getkc id="7" kc_name="EDA"] ... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

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