Are Simulation’s Days Numbered?


Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro Riz... » read more

The Week In Review: Design/IoT


Tools Synopsys unveiled a new custom design solution targeting FinFET layout, introducing visually-assisted routing automation, a built-in design rule checking engine, templates to apply previous layout decisions to new designs, and IC Compiler integration. TSMC certified the new tool for 10nm and 7nm FinFET process technologies. It has also been adopted by STMicroelectronics, GSI Technology... » read more

EDAC Changes Name


The EDA Consortium today changed its name to the Electronic System Design Alliance, a move that expands the group's charter to reflect shifts that have been underway in the chip design world for some time. Those shifts include the growth in IP and an increased focus on software development. Classic EDA, from place and route to synthesis to back-end debug and verification, are still very much... » read more

What Cognitive Computing Means For Chip Design


Cognitive computing. Artificial intelligence. Machine learning. All of these are concepts aim to make human types of problems computable, whether it be a self-driving car, a health care-providing robot, or a walking and talking assistant robot for the home or office. R&D teams around the world are working to create a whole new world of machines more intelligent than humans. Designing sys... » read more

Blog Review: March 30


Are we in a new wave of formal? Mentor's Joe Hupcey III highlights several things from DVCon that indicate formal is becoming a cornerstone of mainstream verification flows. Synopsys' Graham Etchells continues his search for more ways to bring greater efficiency to the FinFET layout process, and the downsides to custom routing solutions. Cadence's Paul McLellan takes a look at TSMC's rapi... » read more

Planes, Cars, And Lagging Standards


Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

The Week In Review: Design/IoT


Numbers EDA sales dropped 1.9% in Q4 of 2015, following a spectacular run of 23 consecutive quarters of solid growth, according to EDAC. For the year, the EDA and IP industry posted 5% growth. At the same time, IP revenue grew 9.2% to $702.2 million, making it the first time ever that IP surpassed CAE revenue. Services revenue also grew 5.4% year over year to 107.1 million. A new report f... » read more

Are Simulation’s Days Numbered?


In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Do Design And Verification Change In The IoT Age?


Where is the Internet of Things (IoT) on the hype curve? Are expectations too high, or is it really the next big thing? My recent trip to the Design Automation and Test Conference (DATE) in Dresden, Germany, did not give all the answers, but it definitely did shed some light for me on this topic. A very enthusiastic taxi driver took me back 25 years to the Nov. 9, 1989, the time when the Ber... » read more

Blog Review: March 23


How exactly does a giant fire behave in space? NASA plans to find out, in the latest top five tech picks from Ansys' Justin Nescott. Plus, never scrape ice off your car again and a pangolin-inspired motorcycle helmet. Cadence's Paul McLellan investigates the growing impact of dark silicon as Dennard scaling breaks down and the number of cores in a chip grows. Mentor's Harry Foster present... » read more

← Older posts Newer posts →