tag: Cadence

Executive Insight: Gideon Wertheizer
By Ed Sperling - 13 Aug, 2014 - Comments: 0

SE: From your standpoint, what’s the next big thing? Wertheizer: The industry was driven in the past few years by the structure the smartphone created. It looks like this area is about to grow. What’s changing is the integration of the smartphone with other applications. The smartphone is now a hub of entertainment and productivity with many devices connecting directly or indirectly to i... » read more

Blog Review: Aug. 13
By Ed Sperling - 13 Aug, 2014 - Comments: 0

Cadence’s Richard Goering interviews Kathryn Kranen about the acquisition of her company, along with the business of formal verification. Interesting tidbit: The combined company has more than 50% market share in formal. Mentor’s John Day looks at Volkswagen’s upcoming all-electric Golf that will go on sale later this year in the United States. The new twist: VW has struck a deal with ... » read more

The Week In Review: Design
By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

IP Reaches Back To Established Nodes
By Ann Mutschler - 07 Aug, 2014 - Comments: 0

Driven by the [getkc id="76" kc_name="IoT"] and wearable market opportunity, [getkc id="81" kc_name="SoC"] developers are shifting backward to established nodes, and what is learned at the leading-edge nodes is being leveraged in reverse as IP is ported backward to improve functionality. [getkc id="43" kc_name="IP"] certainly can be improved to work faster at older geometries, stressed Krish... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Making Software Better
By Ed Sperling - 07 Aug, 2014 - Comments: 0

Gauging the energy efficiency of software is a difficult task. There are many types of software, from embedded code all the way up to software that controls various modes of operation to downloaded applications. Some software interacts with other software, while other software works independently. And some works better on one SoC configuration than another, or on one iteration of an operating s... » read more

Established Nodes Getting New Attention
By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

If It Ain’t Broke, Start Fixing It Right Away
By Brian Fuller - 07 Aug, 2014 - Comments: 0

"If it ain't broke don't fix it." It’s a line that can lull businesses into fatal complacency. It lies at the heart of Harvard Professor Clayton Christensen's innovator's dilemma writings: The products or services driving a successful business "ain't broke," but they usually prevent companies from anticipating or responding to disruptive innovation outside their walls. Our electronics ind... » read more

Test Becomes Power-Aware
By Ann Mutschler - 07 Aug, 2014 - Comments: 0

Power-aware test plans are changing, becoming far more extensive than the minimalist plans that were common just a few years ago. In the past would determine if they could power their design up, power it down, then they’d declare it done. “Sometimes they would find they could power it up and power it down once, but they couldn’t power it up a second time because they’d forgotten to ... » read more

Blog Review: Aug. 6
By Ed Sperling - 06 Aug, 2014 - Comments: 0

Mentor’s Colin Walls takes a look at bad behavior—the undefined kind that you get from doing C programming wrong and adding too much complexity up front. Cadence’s Brian Fuller interviews his colleague about what engineers need to know in regards to finFETs, advanced nodes and parasitic extraction. Short answer: Plenty. Synopsys’ Mick Posner is building FPGA prototype boards and... » read more

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