Designing For Security


Some level of security is required in SoC today, whether it is in hardware, software or — most commonly — both. Of course, there is a price to pay from a power and performance perspective, but thankfully just a small one in most cases. The explosion of consumer devices has driven the need for increased security features in smart cards, smart phones, personal computers, home networks, and... » read more

The Week In Review: Design


Deals Cadence won a deal with Airoha Technology, which will use Cadence’s RTL compiler and test tools to reduce power and test patterns in Bluetooth radio chips. Airoha is a fabless design house based in Taiwan. IP Cadence’s PHY and controller IP for PCI Express 3.0 have passed PCI-SIG certification tests. Numbers NXP reported its Q2 results. Revenue was $1.349 billion, up 14% comp... » read more

Blog Review: July 30


Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes. Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what... » read more

The Week In Review: Design


Tools Sonics upgraded its on-chip network, improving support for memory subsystems as well as performance with guaranteed bandwidth allocation across multiple SOC flows. The company said these upgrades add support for the latest DDR4 and LPDDR4 memories, for the multi-threading capabilities of the Open Core Protocol interface, and while adding non-blocking concurrency technologies. Mentor G... » read more

IP Integration Challenges Rising


It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

EDA’s Hedge Plays


While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

New Winners And Losers


During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

High-Level Gaps Emerge


Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

The Agony Of Hardware-Assisted Development Choices


“When defining a product, if you haven’t upset at least one part of the organization, then the product is probably ill defined and tries to address too many things!” That’s what one of my mentors taught me early on in my career as product manager. Ever since then I have been interested in portfolio management. The most recent announcement that we made on the Protium Rapid Prototyping Pl... » read more

Blog Review: July 23


Mentor’s John Day says that within the decade you will be able to contact a real person from your car. Hopefully that doesn't mean marketing people will be able to contact you while you’re stuck in traffic. Cadence’s Brian Fuller says the future of EDA in the automotive market isn’t just about chips. Think security, software and cost reduction. It’s not just SoCs that are going ... » read more

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