tag: Cadence

Blog Review: Aug. 27
By Ann Mutschler - 27 Aug, 2014 - Comments: 0

In the spirit of making a positive social contribution, and to recognize employees for their contributions to the local community, Applied Materials’ chairman Mike Splinter accepted the ALS Ice Bucket Challenge. Nice job, Mike! With development work underway on the 10nm process node, and questions about getting there with conventional lithography, Cadence’s Richard Goering invites us to ... » read more

Fixing Functional Coverage
By Brian Bailey - 22 Aug, 2014 - Comments: 2

Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Looking For The Next Big Thing
By Brian Bailey - 21 Aug, 2014 - Comments: 0

With [getkc id="74" comment="Moore's Law"] slowing down or coming to an end, finding the next big thing may be very different than it was in the past. We cannot assume that more of the same will be a winner. The semiconductor industry has been blessed with two new product categories that have catapulted it through what should have been a very difficult period with barely a scratch. Those techno... » read more

The Changing IP Ecosystem
By Ann Mutschler - 21 Aug, 2014 - Comments: 0

Is a larger [getkc id="43" kc_name="IP"] company better suited to deliver what users need – from hardware to software to PDKs and reference designs – with larger and more diverse teams to draw upon, as well as deep foundry relationships? Or does it pay to small, quick and nimble? The answer to that question appears to be playing out in real time. As design complexity has increased, so ha... » read more

More Than Moore
By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

Different Approaches Emerge For Stacking Die
By Ed Sperling - 21 Aug, 2014 - Comments: 1

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

EDA Suffering Funding Crisis
By Brian Bailey - 21 Aug, 2014 - Comments: 5

The EDA industry has been built on venture funding ever since its inception in the early eighties and it is no secret that the big three have relied on a steady stream of startup companies to provide some of the new ideas, to test out new technologies and expand the industry. While there is a lot of research and development that goes on inside the large companies, most of this is related to ... » read more

When To Virtualize, When To Stay In The Real World
By Frank Schirrmeister - 21 Aug, 2014 - Comments: 0

Virtualization is all the craze these days. People have virtual personas on LinkedIn, Facebook and Match. I sent my daughter to a Minecraft camp at Stanford where she built virtual worlds while learning programming. Virtualization also plays an important role in chip development, especially when it comes to representing the system environment. There is, however, some crass misinformation out th... » read more

Blog Review: Aug. 20
By Ed Sperling - 20 Aug, 2014 - Comments: 0

Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Check out the “Sprouting Baby Monitor.” This may be a sign of what the IoT is really good for. You can also use your cat (or dog or even your kids) to hack your neighbor’s Wi-Fi. Cadence’s Richard Goering says gaps may be narrowing between available tools and what’s needed for 3D-IC design. Now all w... » read more

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

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