tag: Cadence

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: Has the move to 20nm processes with 14nm finFETs progressed as smoothly as everyone hop... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Mixing It Up
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Cost Per Transistor Gets Fuzzier
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

Changes In The Supply Chain
By Ed Sperling - 31 Jan, 2013 - Comments: 0

Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it. Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density... » read more

Mixed-Signal Technology Summit Proceedings
By Various Writers - 31 Jan, 2013 - Comments: 0

On September 20 Cadence held the second Mixed-Signal Technology Summit. Experts from Cadence and other leading companies presented the latest mixed-signal design methodologies. If you missed the event, you can still view the material via the below archived proceedings. To view the presentations and videos, click here. » read more

It’s The Data, Stupid!
By Frank Schirrmeister - 30 Jan, 2013 - Comments: 0

By Frank Schirrmeister January is prediction month! After writing my 10 year Look-Back on Technology last week, I attended an IDC briefing called “Riding the Momentum: IDC Software Predictions 2013.” IDC is looking at the IT world from four angles that they call four pillars: Cloud, Big Data/Analytics, Social Business and Mobility. In the opening presentation—called “In a Diverse Wo... » read more

ESL Challenges
By Ed Sperling - 26 Jan, 2013 - Comments: 0

System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Reducing The Drama In DFM
By Ed Sperling - 24 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes. The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, se... » read more

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