tag: Cadence

LP Test
By Luke Lang - 11 Oct, 2012 - Comments: 0

By Luke Lang Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time. Typically, a chip’s power grid is designed to meet IR drop specification in the func... » read more

Experts at the Table: Black Belt Power Management
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss rising integration challenges caused by an increasing amount of black-box IP with Qi Wang, technical marketing group director, solutions marketing, for the low-power and mixed-signal group at Cadence; J. Bhasker, architect at eSilicon Corp.; Navraj Nandra, senior director of product marketing for analog an... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Where Does It Hurt?
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The IC design industry is feeling a new kind of pain—this one driven by uncertainty over architectural shifts, new ecosystem interactions and new ways to account for costs. As mainstream ICs move from 50/45/40nm to around 32/28/22nm, there are only two choices for design teams—continue shrinking features or stack dies. In many cases, the ultimate solution may be a combina... » read more

Like Oil And Water
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler For years, the promise and allure of a concurrent design methodology included talk of models, high-level synthesis, virtual prototyping and other system-level technologies all peacefully coexisting in a single design methodology. While it sounds like a good idea, the model-based design approach hasn’t mixed well with the virtual prototype approach. And at l... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

On Design Productivity And Cost of Ownership …
By Frank Schirrmeister - 25 Sep, 2012 - Comments: 0

By Frank Schirrmeister Last weekend I spent time with my 7 ½-year-old daughter (the ½ is crucially important at that age) on our tree house project. Well, it is more a tree “deck” so far, which is quite respectable though given that we just started building it in one weekend (as the book I quickly downloaded that evening on the iPad actually recommended). A project like this gives endles... » read more

Power And Performance: GSS Sees SOI Advantages For FinFETs
By Various Writers - 17 Sep, 2012 - Comments: 0

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI. To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s... » read more

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

LP Test Strategies
By Luke Lang - 13 Sep, 2012 - Comments: 0

By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

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