tag: Cadence

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 04 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Gap Vs. Gap
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

Rethinking Timing Optimization
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node. “With lower nodes we are getting advantage on area, more and more logic is get... » read more

Boosting Yield With Layout Awareness
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

Roundtable: Bridging Hardware And Software
By Ed Sperling - 25 Apr, 2012 - Comments: 0

System-Level Design talks about where the problems are with hardware-software co-design and how much progress we've made with Narendra Konda of Nvidia, Frank Schirrmeister of Cadence, Shabtay Matalon of Mentor Graphics, Kurt Shuler of Arteris and Jack Greenbaum of Green HIlls Software. [youtube vid=EOUPsDOYGq8] » read more

Picking The Right Processor
By Frank Schirrmeister - 24 Apr, 2012 - Comments: 1

By Frank Schirrmeister In an embedded system, the sole connection point between the software and the hardware is the processor. Somewhere right now the effort to develop software for a complex System-on-Chip (SoC) is surpassing the effort of developing the chip itself. As I pointed out in my recent description of the Design West conference in San Jose, complex ecosystems of related content, to... » read more

Betting On Subsystems
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling One of the consistent trends among successful companies, particularly in well-established industries, is that over time labor becomes specialized. No one can do everything well, and the more complex the systems the more pieces have to be outsourced. This creates immediate benefits for companies putting together the overall systems. They can focus on designs and doing what the... » read more

2.5D Leverages Existing Tools On The Way To 3D
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield. Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase,... » read more

Reliability Concerns Grow
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling Knowing when to signoff on an IC design has always been as much art as science, matching engineering experience with managed risk. As ICs become more complex, however, even the most advanced chip companies are getting things wrong. Some of this can be fixed through software and some of it can be tweaked with programmable firmware. But some of it may have to be fixed in the ne... » read more

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