tag: Cadence

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

EDA’s Cloudy Vision
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Since the dawn of EDA, the industry has largely operated under a traditional software distribution model whereby the customer would run the software it licensed on its own hardware equipment. With the sophistication of advanced IT management techniques as well as education surrounding “The Cloud,” it may be safe to predict that engineers in the not-to-distant futu... » read more

System-Level Models Redefined
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler It wasn’t that long ago that the promise of system-level models was an easy implementation path and the ability to then reuse the models in a different design, for a different target application. But how reusable are those models in reality? The answer depends on whom you ask. First, it is important to define what a system-level model is, noted Frank Schirrmeiste... » read more

UVM Do’s And Don’ts For Effective Verification
By Various Writers - 24 May, 2012 - Comments: 0

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, producing UVM 1.1 and 1.1a bug-fix versions, as well as created a wealth of institutional know-how. Of course, the challenge with know-how is that it tends to be distributed among all the members of the c... » read more

Endless Abstractions?
By Frank Schirrmeister - 22 May, 2012 - Comments: 1

By Frank SchirrmeisterHaving started my own career doing full custom layout, then moving though gates and RTL to transactions and embedded software, I always was a little bit concerned whether the industry would eventually run out of abstraction levels for me to adopt further upwards. It looks like there is plenty of head room.Last week I was in Munich attending the CDNLive! EMEA event. I was h... » read more

Technology Crossover Ahead
By Ed Sperling - 18 May, 2012 - Comments: 0

The attention showered upon NVM Express these days by both Synopsys (verification IP) and Cadence (subsystem) is significant. It’s the first significant opening in the enterprise computing space to emerge in years, and this is a market in which efficiency and performance are both measured and fully recognized. While SoC developers in the mobile space continue to develop power-management ca... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 11 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

Old Problem, New Solutions
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events. “These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Ment... » read more

Traversing The Abstraction Landscape
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

LP Macros
By Luke Lang - 10 May, 2012 - Comments: 0

By Luke Lang Many designers have asked why CPF has the macro model commands while UPF/1801 does not. I will try to answer this question and explain the differences in both approaches. First, let’s briefly review CPF macro model. A CPF macro model describes the power interface of a macro cell, which could be a complex cell (pad cell), an IP block (memory), or a hardened block (ARM core). F... » read more

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