tag: Cadence

How Firm Is Firmware?
By Frank Schirrmeister - 26 Jun, 2012 - Comments: 0

By Frank Schirrmeister When blogging recently about Xilinx’s presentation at the Cadence DAC 2012 EDA360 theater, which was given by Dave Beal, I ran across the diagram he had used to outline the “development stack” from hardware to software. Dave had described a virtual prototype to the audience as a functional model that recreates the WHAT rather than the HOW, duplicating the result ... » read more

What’s ST’s FD-SOI Technology All About?
By Various Writers - 22 Jun, 2012 - Comments: 0

As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ... » read more

Reducing Circuitry To Reduce Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Power Shift
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling For the past decade, most of the real gains in energy efficiency were developed for chips inside mobile electronics because of the demand for longer battery life. Dark silicon now represents the majority of mobile devices, multiple power islands are commonplace to push many functions into deep sleep, and performance is usually the secondary concern for most applications. Whil... » read more

Getting Formal With Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling Formal methodologies have always been an important tool in the verification engineer’s toolbox because they often can pinpoint bugs faster and with more accuracy than other verification approaches. The problem is that most engineers don’t know how to use them, and understanding this technology to a proficiency level requires a learning curve that most engineers consider pain... » read more

LP Macros 2
By Luke Lang - 14 Jun, 2012 - Comments: 0

By Luke Lang Last month, I compared the CPF macro model with LP attributes in the Liberty model. The CPF macro model was developed when Liberty had very little LP attributes to support LP designs. Even today, Liberty still lacks LP attributes to describe some of the common power intent in LP designs. One example is an LP IP block with internal power switches and shutoff domains. Because mos... » read more

Power Modeling: Use Cases Need to be Clearly Defined
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss power modeling during the Design Automation Conference with Vic Kulkarni, senior vice president and general manager at Apache Design; Paul Martin, design enablement and alliances manager at ARM; Sylvan Kaiser, CTO at Docea Power; and Frank Schirrmeister, group director, product marketing for system deve... » read more

Experts At The Table: Black Belt Power Management
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

Executive Briefing: Orchestrating Change In IC Design
By Ed Sperling - 31 May, 2012 - Comments: 0

Cadence CEO Lip-Bu Tan sounds off to System-Level Design about what's changing in EDA, in Cadence, in the supply chain, and the need to make it all work together. [youtube vid=iwl5HOs4UsU] » read more

The Brave New World Of Modeling TSVs
By Ed Sperling - 26 May, 2012 - Comments: 0

By Ann Steffora Mutschler With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together... » read more

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