tag: Cadence

Power, Applications Drive New Thinking On System Planning
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Throwing out the term ‘application-driven power-aware design methodology’ may sound like gobbledygook to some, but this concept is keeping many technologists awake at night—especially considering video games that heat iPads to 100+ degrees centigrade (near melting). The problem is very real, and potentially painful in more ways than one. The iPad example, al... » read more

Getting Ready For Stacked Die
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary. All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, A... » read more

Experts At The Table: Designing At 28nm And Beyond
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and... » read more

Fundamentals For 3D IC Flows
By Ann Mutschler - 05 Apr, 2012 - Comments: 0

While true 3D ICs are a few years off, 2.5D is here. There are some key differences, namely that with 2.5D the interposer is a passive die, but there also are some fundamental shared requirements. Samta Bansal, senior product marketing for Silicon Realization at Cadence asserted that first, the digital, custom and package environments must be seamless. “There has to be a co-design between ... » read more

Experts At The Table: Designing At 28nm And Beyond
By Ed Sperling - 30 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

Enterprise Power
By Ed Sperling - 30 Mar, 2012 - Comments: 0

The corporate data center is getting a lot of attention these days. ARM is fighting for a place inside server racks. Cadence has rolled out IP for faster storage standards. And Mentor Graphics has just introduced middleware for embedded Linux. Why? Because unlike the mobile space, where you need billions of units to make margins, in the corporate enterprise you only need millions. Those extr... » read more

Experts At The Table: IP
By Ed Sperling - 23 Mar, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: The su... » read more

Experts At The Table: Designing At 28nm And Beyond
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), an... » read more

Coherency Becomes A Stack Of Issues
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design. There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even mo... » read more

The Software Side Of Derivatives
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler With the options and perils associated with derivative designs well articulated today, the elephant remaining in the room is, of course, software. The software aspect of derivatives is bit muddier with some claiming the software can be maintained without modification, while others assert this is simply not possible. One indisputable fact is that software develop... » read more

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