tag: debug

The Race For Better Verification
By Graham Bell - 21 Nov, 2013 - Comments: 0

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Experts At The Table: Debug
By Ed Sperling - 31 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

How Much Verification Can One Engineer Handle?
By Frank Schirrmeister - 25 Sep, 2013 - Comments: 0

By Frank Schirrmeister When reviewing the agenda of our upcoming Verification Summit here in San Jose this Thursday, the question came to mind of who can actually execute the required complex verification tasks. Can they understand enough detail in hardware, software, and the system aspects to efficiently rid the design of bugs? The reality is that the task requires not one engineer who can do... » read more

Power-Up Low-Power Verification
By Adam Sherer - 09 May, 2013 - Comments: 0

By Adam Sherer When facing low-power verification in the SoC world, everyone could use a few power-ups just like Nintendo’s little plumber, Mario. Sure, Mario could run and jump through a lot of terrain, but when he hit some new challenges he could rely on some new tools and techniques to get him through. Completing your first SoC with a single power control module (PCM) and domain is lik... » read more

Executive Briefing: Wally Rhines
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design, as part of its ongoing executive briefing series, sat down with Wally Rhines, Mentor Graphics' chairman and CEO, to talk about future problems, opportunities, and the gray areas that could go either way. What follows are excerpts of that conversation. SLD: Is the amount of time spent on verification increasing? Rhines: It depends on how you define who s... » read more

The Seven Layers Of Hardware-Software Debug
By Frank Schirrmeister - 22 Aug, 2012 - Comments: 0

By Frank Schirrmeister [caption id="attachment_9863" align="alignnone" width="639"] Seven Layers of Hardware/Software Debug[/caption] Of course I will be in trouble once this blog is posted. This post is about hardware/software debug,  and I tried to layer a set of different levels for the scope and applicability of debug. I counted seven layers, but I am sure that one may be able to arr... » read more

Pest Control
By Achim Nohl - 17 Nov, 2011 - Comments: 0

By Achim Nohl Identifying and describing power issues is tough, let alone trying to solve them. “Power” issues can be very diverse. It’s even more difficult to explain how virtual prototypes can help to analyze “power” consumption. We often approach it by introducing how power information can be reflected in virtual prototype models, but there are many different goals and conflicting... » read more

Best Practices For Multicore SoC Test And Debug
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

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