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Chasing Test Escapes In IC Manufacturing


The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

Is The Stacked Die Ecosystem Stagnating?


It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more