CXL Picks Up Steam In Data Centers

By Marie C. Baca - 26 Jan, 2023 - Comments: 0

CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

Greener Design Verification

By Brian Bailey - 27 Jan, 2022 - Comments: 0

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, or power consumption. Admittedly, one is a per unit cost while the other is a development cost, but could the industry be doing more to make development greener? It can take days for regression... » read more

Creating Better Models For Software And Hardware Verification

By Ed Sperling - 04 Aug, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Simplifying And Speeding Up Verification

By Ed Sperling - 16 Jun, 2020 - Comments: 1

What Will The Next-Gen Verification Flow Look Like?

By Ed Sperling - 28 May, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; and Nasr Ullah, senior director of performance architecture at SiFive. What follows are exc... » read more

Revving Up For Edge Computing

By Ed Sperling - 07 Nov, 2019 - Comments: 1

The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

Dell EMC Ready Solutions for HPC Digital Manufacturing – ANSYS Performance

By Ansys - 11 Sep, 2019 - Comments: 0

This technical white paper describes the performance of ANSYS Fluent, Mechanical, and CFX on the Dell EMC Ready Bundle for HPC Digital Manufacturing, which was designed and configured specifically for Digital Manufacturing workloads, where Computer Aided Engineering (CAE) applications are critical for virtual product development. In addition, the architecture of the Dell EMC Ready Bundle for HP... » read more

System Bits: Sept. 11

By Jeff Dorsch - 11 Sep, 2019 - Comments: 0

Everything’s faster in Texas The Frontera supercomputing system was formally unveiled last week at the Texas Advanced Computing Center. The system was deployed in June on the University of Texas at Austin campus. It is the fifth-fastest supercomputer in the world at present and the world's fastest academic supercomputer. Dell EMC and Intel collaborated on fitting out Frontera. Work beg... » read more

Challenges To Building Level 5 Automotive Chips

By Ann Mutschler - 05 Sep, 2019 - Comments: 0

It’s an exciting time in the automotive space, and this is especially true when it comes to all of the activity around autonomous driving and the path to achieving full Level 5 autonomy. The technology is complex, the ecosystem seems to get more complex by the day, and simulating autonomous systems safely makes this an extremely fascinating area from an engineering perspective. At the heart o... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 10 May, 2019 - Comments: 0

Internet of Things Microsoft this week introduced IoT Plug and Play, a no-code toolkit for connecting Internet of Things devices to the cloud. The company touts it as a new modeling language to pump up the capabilities of IoT devices through the Microsoft Azure cloud service. The Azure IoT Device Catalog lists devices that support IoT Plug and Play, such as the STMicroelectronics SensorTile.bo... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Dell EMC