tag: EDA

Is The IP Industry Healthy?
By Brian Bailey - 13 Jul, 2017 - Comments: 0

The semiconductor industry has been through many changes, each designed to reduce the total cost associated with the design and manufacture of chips. Twenty years ago, most companies had their own fabs and designed all of the circuitry on each chip. Today, only a handful of companies still own a fab and outsourcing design, in the form of intellectual property ([getkc id="43" kc_name="IP"]), has... » read more

Implementing High-Density-Advanced Packaging for OSATs And Foundries
By Mentor, a Siemens Business - 12 Jul, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

EDA, IP Growth Hits Double Digits
By Ed Sperling - 06 Jul, 2017 - Comments: 0

The cloud, advanced packaging and AI/machine learning pushed up EDA and IP revenue to the highest Q1 growth level since 2011. Revenue was up 10.5% year over year to $2.168 billion, compared with $1.962 billion in Q1 2016, according to just-released numbers from the Electronic System Design (ESD) Alliance. The four-quarter moving average increased by 10.6%. The two largest regions, the Americ... » read more

EDA Moves Out Of The Shadows
By Ed Sperling - 29 Jun, 2017 - Comments: 0

EDA has long harbored ambitions that are larger than a piece of silicon. The engineering challenges being solved on a nanometric scale are remarkably similar to ones being solved at a much higher level—architectural design, layout, validation, verification, debug, thermal mapping, and a lot more. The problem, at least until recently, is that it has been difficult to gain a foothold in larg... » read more

Machine Learning Meets IC Design
By Brian Bailey - 29 Jun, 2017 - Comments: 2

Machine Learning (ML) is one of the hot buzzwords these days, but even though EDA deals with big-data types of issues it has not made much progress incorporating ML techniques into EDA tools. Many EDA problems and solutions are statistical in nature, which would suggest a natural fit. So why is it so slow to adopt machine learning technology, while other technology areas such as vision recog... » read more

Hybrid Emulation
By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Monday At DAC
By Brian Bailey - 20 Jun, 2017 - Comments: 1

The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

Safety Plus Security: A New Challenge
By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Chip Test Shifts Left
By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

What’s Next In Scaling, Stacking
By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

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