The Darker Side Of Hybrid Bonding


With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

A Renaissance For Semiconductors


Major shifts in semiconductors and end markets are driving what some are calling a renaissance in technology, but navigating this new, multi-faceted set of requirements may cause some structural changes for the chip industry as it becomes more difficult for a single company to do everything. For the past decade, the mobile phone industry has been the dominant driver for the semiconductor eco... » read more

Week In Review: Manufacturing, Test


Semicon recap The virtual version of Semicon West took place this week. Virtual events have their places. It’s no substitute for an in-person event. Nonetheless, the virtual version of Semicon West is still a place to get an update on the latest equipment, test and packaging technologies. It is also interesting to visit the virtual booths. It’s a fast way to meet people. I chatted with ... » read more

The Race To Much More Advanced Packaging


Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Manufacturing Bits: March 3


Security lithography At the recent SPIE Advanced Lithography conference, Multibeam disclosed more details about its efforts to develop multi-beam direct-write lithography for chip security applications. David Lam, chief executive and chairman of Multibeam, described how multi-beam lithography can be used to help thwart IC counterfeiting and tampering in the market. This lithography technolo... » read more

Brighter Future For Photonics


Photons increasingly are taking over where electrons are failing in communications, but mixing the two never has been easy. There always have been two potential implementation paths — building each on its own substrate and then stacking them, or building them on a single substrate. The tradeoff between the two solutions is more complex than it may initially appear, and ongoing improvements... » read more

New Trends In Wafer Bonding


Unable to scale horizontally, due to a combination of lithography delays and power constraints, manufacturers are stacking devices vertically. This has become essential as the proliferation of mobile devices drives demand for smaller circuit footprints, but the transition isn't always straightforward. Three-dimensional integration schemes take many forms, depending on the required interconne... » read more

Manufacturing Bits: Oct. 22


3.5D chip packaging In a recent paper, PacTech has described a vertical laser assisted bonding process for use in developing advanced 3.5D chip packages. Laser assisted bonding (LAB) is an interconnection technology used in IC packaging. It uses a laser as a thermal energy, which in turn connects a die bump and a substrate pad, according to Amkor, which is the original developer of LAB tech... » read more

The Race To Next-Gen 2.5D/3D Packages


Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Week In Review: Manufacturing, Test


Chipmakers GlobalFoundries has filed suits in the U.S. and Germany, alleging that semiconductor manufacturing technologies used by TSMC infringe upon 16 of GF's patents. The suits were filed in the U.S. International Trade Commission (ITC), the U.S. Federal District Courts in the Districts of Delaware and the Western District of Texas, and the Regional Courts of Dusseldorf and Mannheim in Germ... » read more

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