Doing More With RTL Power Analysis: Smart Synthesis Architecture


Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Pathfinding Beyond 10nm


After higher aspect-ratio finFETs and higher mobility SiGe and III-V materials, the industry will move to lateral nanowires and then to vertical nanowire transistors, and to new tunnel junction FETs or spin wave architectures ─ or to various combinations of these technologies for different applications, reported An Steegan, Imec senior vice president of process technology, during SEMICON West... » read more

Executive Insight: Aart de Geus


Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

Reliability After Planar Silicon


Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

The Great Imbalance


The number of options for chipmakers is growing while the number of chipmakers is shrinking. So what does this mean for the semiconductor industry? Short answer: No one is quite sure yet. But a lot more people are beginning to ask that question these days, including investors and analysts. There are a number of factors at play here. To begin with, there are more nodes to choose from than at ... » read more

Inside Samsung’s Foundry Biz


Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at [getentity id="22865" e_name="Samsung Semiconductor"]; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion. SE: The foundry business has alway... » read more

Challenges At Advanced Nodes


Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Surprises At SEMICON West


As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about. Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that are driving growth and excitement at semiconductor equipment... » read more

Power Breaks Everything


The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Tech Talk: 22nm FD-SOI


Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

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