Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

By Sergio Marchese - 28 Mar, 2019 - Comments: 0

Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. In addition, participants had to prove that... » read more

Utilizing More Data To Improve Chip Design

By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

Formal Apps Take The Bias Out Off Functional Verification

By Mentor, a Siemens Business - 27 Mar, 2019 - Comments: 0

The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

Fixing Functional Coverage

By Brian Bailey - 22 Aug, 2014 - Comments: 2

Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: formal analysis

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

Utilizing More Data To Improve Chip Design

Formal Apps Take The Bias Out Off Functional Verification

Fixing Functional Coverage