tag: GlobalFoundries

Materials, Magnetism & Quantum Physics
By Ed Sperling - 21 Jun, 2018 - Comments: 0

For the past half-century, chipmakers have been following the same roadmap for improving performance in chips and reducing the cost of chips. That has proven tremendously effective in reducing costs and packing computing into a smaller space, allowing people to carry around what used to be a multi-million-dollar mainframe in their pocket. That approach is beginning to lose momentum. It's ge... » read more

System-In-Package Vs. eNVM
By Yafeng Zhang - 21 Jun, 2018 - Comments: 0

The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%. Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but al... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Tech Talk: Connected Intelligence
By Ed Sperling - 21 Jun, 2018 - Comments: 0

Gary Patton, CTO at GlobalFoundries, talks about computing at the edge, the slowdown in scaling, and why new materials and packaging approaches will be essential in the future. https://youtu.be/Zbz0R_yFFrQ » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

CMOS-Embedded STT-MRAM Arrays In 2xnm Nodes For GP-MCU Applications
By GlobalFoundries - 20 Jun, 2018 - Comments: 0

Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full a... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 15 Jun, 2018 - Comments: 0

Chipmakers and OEMs Tesla Motors has been struggling to get its new electric car, the Model 3, out the door. And it recently implemented a layoff amid ongoing losses. But the struggling car maker could be in the midst of a rebound. “Based on our checks, we believe the perceived quality of Model 3s coming off the lines continue to improve relative to prior checks, and we view this as one of t... » read more

Chip Dis-Integration
By Brian Bailey - 14 Jun, 2018 - Comments: 2

Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

Advanced Packaging Confusion
By Ed Sperling - 13 Jun, 2018 - Comments: 2

Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and 2.5D. But as chipmakers began understanding the difficulty, cost and reduced benef... » read more

New Transistor Types Vs. Packaging
By Ed Sperling - 11 Jun, 2018 - Comments: 0

Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren't enough chips in the world to support all of them profitably. FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and... » read more

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