EMEA Investments Driving Technology Specialization


Government programs across Europe and the UK are seeing a surge of investments in leading edge technology, materials, and packaging. Industry and academia are coalescing around specialty areas, drawing on established relationships to foster innovation and fill gaps in regional supply chains while also maintaining international bonds. Government initiatives also are picking up in Israel, Saudi A... » read more

Chip Industry Week In Review


Siemens announced plans to acquire Altair Engineering, a provider of industrial simulation and analysis, data science, and high-performance computing (HPC) software, for about $10 billion. Altair's software will become part of Siemens' Xcelerator portfolio and provide a boost to physics-based digital twins. Onto Innovation bought Lumina Instruments, a San Jose, California-based maker of lase... » read more

2D Semiconductors Make Progress, But So Does Silicon


Semiconductor industry researchers have been anticipating the need for better transistor channel materials to replace silicon for a long time, but silicon devices have continued to improve enough to postpone that change. Silicon continues to provide an unmatched combination of device performance, manufacturability, and cost effectiveness. In recent years, though, the “end of silicon” cha... » read more

The Impact of Magnetic Fields On STT-MRAM Operations


A technical paper titled "Impact of external magnetic fields on STT-MRAM" was recently published by researchers at Univ. Grenoble Alpes, Everspin, GlobalFoundries, imec, et al. Abstract "This application note discusses the working principle of spin-transfer torque magnetoresistive random access memory (STT-MRAM) and the impact that magnetic fields can have on STT-MRAM operation. Sources of... » read more

Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Hybrid Bonding Makes Strides Toward Manufacturability


Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results. Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But whil... » read more

Chip Industry Week In Review


Europe's top court ruled in Intel's favor, voiding a $1.1 billion fine imposed by the European Union and dismissing charges of anti-competitive behavior. IBM released yield benchmarks for high-NA EUV, which serve as proof points that the newest advanced litho equipment will enable scaling beyond the 2nm process node. Also on the lithography front, Nikon is developing a maskless digital litho... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)


A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

Chip Industry Week In Review


Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs


Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

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