tag: Intel

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Manufacturing Bits: April 21
By Mark LaPedus - 21 Apr, 2015 - Comments: 0

Fan-out packaging consortium A*STAR’s Institute of Microelectronics (IME) and others have formed a high-density fan-out wafer level packaging (FOWLP) consortium in Singapore. Others in the group include Amkor, Nanium, STATS ChipPAC, NXP, GlobalFoundries, Kulicke & Soffa, Applied Materials, Dipsol Chemicals, JSR, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo (TOK). T... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 17 Apr, 2015 - Comments: 0

It could be a long year for the equipment industry. First, Intel reduced its 2015 capital expenditure budget to $8.7 billion, plus or minus $500 million. This is down from the previous mid-point guidance of $10.1 billion. As a result of Intel’s announcement, Pacific Crest Securities cut its worldwide 2015 semiconductor CapEx forecast. The new CapEx forecast is now $62.5 billion in 2015. Th... » read more

New Patterning Paradigm?
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

Next EUV Challenge: Mask Inspection
By Mark LaPedus - 16 Apr, 2015 - Comments: 2

Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

FinFET Rollout Slower Than Expected
By Mark LaPedus - 16 Apr, 2015 - Comments: 1

The foundry business is heating up as some new and large players are entering the 16nm/14nm [getkc id="185" kc_name="finFET"] market. But foundry customers are taking longer than expected to migrate to finFETs amid some technical and cost issues. On the foundry front, [getentity id="22846" comment="Intel"] has been the sole player in finFETs for some time. But now, [getentity id="22865" ... » read more

5 Issues Under The Foundry Radar
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

In the foundry business, the leading-edge segment grabs most, if not all, of the headlines. Foundry vendors, of course, are ramping up 16nm/14nm finFET processes, with 10nm and 7nm in R&D. The leading-edge foundry business is sizable, but it’s not the only thing going on in the competitive arena. In fact, there are battles taking place in many other foundry segments, such as 2.5D/3D packag... » read more

One-On-One: Dark Servers
By Katherine Derbyshire - 14 Apr, 2015 - Comments: 1

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. To... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 10 Apr, 2015 - Comments: 1

Intel is quietly delaying its process ramp at the 10nm node, according to multiple sources. In an e-mail, a spokesman for Intel said: “We have not disclosed a schedule for our 10nm process and we won't engage in speculation about it.” In March, though, Intel was supposed to make fab tool buys for high-volume manufacturing at 10nm, sources said. But now, those purchases won’t happen... » read more

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