Blog Review: Oct. 5


Mentor's Michael White explores why established nodes are experiencing such an unexpectedly long lifespan and how that is driving new challenges for designers. Cadence's Ann Keffer checks out the history of Ethernet and how it won the battle to become the dominant network protocol. Is your IoT device fueling a botnet? Vulnerable firmware on internet connected devices was behind one of the... » read more

Design Process Technology Co-Optimization For Manufacturability


Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. Meeting yield and product cost targets is a continuous challenge, due to new device structures and increasingly complex process innovations introduced to achieve improved product performance at each new technology node. Design for manufacturability (DFM) and design process technology... » read more

Mask Maker Worries Grow


Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Sorting Out Next-Gen Memory


In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography


Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

The Week In Review: Manufacturing


Chipmakers The finFET market is heating up. GlobalFoundries, Intel, Samsung and TSMC are ramping 16nm/14nm finFETs. And 10nm and 7nm finFETs are in the works. The market will shortly have a new competitor—Taiwan’s United Microelectronics Corp. (UMC). Some years ago, UMC licensed finFET technology from IBM. UMC has been a bit quiet about the 14nm finFET technology, but it has made si... » read more

Blog Review: Sept. 14


Are wide bandgap lll-V power devices feasible? Applied's Ben Lee considers the challenges, and potential rewards, of silicon carbide and gallium nitride. DVCon India chair Gaurav Jalan chats with keynote speaker Alok Jain about the challenges of verifying complex SoCs, the unique verification needs of the IoT, and what might lie beyond UVM. From power intent abstraction to automatic power... » read more

The Week In Review: Manufacturing


Chipmakers GlobalFoundries has rolled out its next-generation FD-SOI technology. The new 12nm FD-SOI process is called 12FDX. It is designed for a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. "Some applications require the unsurpassed performance of finFET transistors, but the vast majority of connected devices need high l... » read more

The Week In Review: Manufacturing


Numbers IC Insights predicts TowerJazz and SMIC sales will jump this year, with the total pure-play foundry revenue forecast to grow 9%. That compares with 6% growth last year. TSMC is expected to shrink slightly to 58% market share, with GlobalFoundries staying flat at 11%. UMC will remain in third place in the rankings, followed by SMIC and TowerJazz. SEMI’s book-to-bill ratio jumped to... » read more

Faster Time To Yield


Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

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