A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)


A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Limiting AI/ML Tools To Ensure Physical AI Safety, Security


Key Takeaways: AI-based tools can help monitor physical AI systems and LLMs, but human oversight is still needed to avoid false positives, bias, and other anomalies. For autonomous vehicles and robots, edge case scenarios and understanding human values are weak points, especially as moral and social values change over time. AI tools are growing and becoming increasingly helpful for c... » read more

Survey of GenAI Across the Full Computing Stack, From SW To Silicon (Harvard)


Harvard University researchers published "GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon." Abstract "Generative AI is reshaping how computing systems are designed, optimized, and built, yet research remains fragmented across software, architecture, and chip design communities. This paper takes a cross-stack perspective, examining how generative models... » read more

The On-Device LLM Revolution


The AI world is experiencing a fundamental shift. After years of cloud-centric inference dominated by massive data center GPUs, we're witnessing an accelerating migration of language models to edge devices. These are not the trillion-parameter behemoths that require server farms, but the "Goldilocks zone" models: 3B to 30B parameters — large enough to deliver genuinely useful AI capabilities,... » read more

LLM-Based Learning Platform For Chip Design Education (RPTU)


RPTU University of Kaiserslautern-Landau researchers published "From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs." Abstract "This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform... » read more

Scaling llama.cpp On Neoverse N2: Solving Cross-NUMA Performance Issues


This blog post explains the cross-NUMA memory access issue that occurs when you run llama.cpp in Neoverse. It also introduces a proof-of-concept patch that addresses this issue and can provide up to a 55% performance increase for text generation when you run the llama3_Q4_0 model on the ZhuFeng Neoverse system. Cross-NUMA memory access problem In llama.cpp, performance drops when the number o... » read more

Benchmark For AI-Aided Chip Design That Evaluates LLMs Across 3 Critical Tasks (UCSD, Columbia)


Researchers at UCSD and Columbia University published "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design." Abstract "While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs' performance in real industrial workflows. To address t... » read more

Balancing Training, Quantization, And Hardware Integration In NPUs


Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

LLM- Based Techniques To Support Behavior-Driven Development For HW Design (U. of Bremen, DFKI)


A new technical paper titled "LLM-based Behaviour Driven Development for Hardware Design" was published by researchers at University of Bremen/DFKI. Abstract "Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineerin... » read more

Data-Centric ML Compiler For PIM (U. of Toronto, Barcelona Supercomputing Center, ETH Zurich, Max Planck)


A new technical paper titled "A Tensor Compiler for Processing-In-Memory Architectures" was published by researchers at University of Toronto, Barcelona Supercomputing Center, ETH Zurich, and the Max Planck Institute for Software Systems. Abstract "Processing-In-Memory (PIM) devices integrated with high-performance Host processors (e.g., GPUs) can accelerate memory-intensive kernels in Ma... » read more

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