tag: Mentor Graphics

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

Power On
By Barry Pangrle - 02 Dec, 2010 - Comments: 0

By Barry Pangrle Process development is more challenging at each successive technology node but the march forward, for the time being, continues unabated. Voltage scaling stopped around the 100nm node at roughly 1.0v as threshold voltages stopped shrinking in an attempt to keep leakage in check. It’s been the progression to the newer and smaller technology nodes that has really pushed power ... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

3D Stacked Die Create Unique Test Issues
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple. There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And... » read more

Building Up In 3D
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

Out Of Context
By Jon McDonald - 18 Nov, 2010 - Comments: 0

By Jon McDonald A rose by any other name is still a rose. I have had the opportunity to speak with a number of different groups recently, covering everyone from systems engineers focused on specifications and documentation to software teams, architects and implementation groups. Each group has their own unique language, their own unique way of communication. Some of the most entertaining co... » read more

Power To Fly
By Barry Pangrle - 04 Nov, 2010 - Comments: 0

By Barry Pangrle As technologies mature, they often follow similar profiles. Back on Oct. 14th I heard Lesley Curwen of the BBC interviewing Charles Champion, executive vice president of engineering at Airbus. Champion said that over the last 40 years the airline industry has reduced emissions and fuel burn by 70%. He pointed out that the industry initially focused on speed and the tendency no... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

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