Ensure Functional Safety Using Siemens’ AUTOSAR Solutions


As the prevalence of automated driving, electrification, and connected vehicle applications increases, the complexity of electrical and electronic (E/E) vehicle architecture is increasing, and vehicle safety requirements are becoming more demanding. Solution architects and engineers are looking for ways to manage it all. And they can, with the help of our comprehensive AUTOSAR solution that pro... » read more

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster


By Nermeen Hossam and John Ferguson Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a chip is DRC-clean to start their chip assembly and verification. Today’s SoC designers typically start chip integration in parallel with block development.... » read more

Verification Scorecard: How Well Is The Industry Doing?


Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Is There A Limit To The Number of Layers In 3D-NAND?


Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

Blog Review: Aug. 24


Synopsys' Manuel Mota presents an overview of some of the newest multi-chip module packaging types and their advantages and disadvantages for different kinds of applications, as well as the importance of die-to-die interfaces. Cadence's Steve Brown finds that innovative products require that electronics be analyzed in the context of the environment in which they run, making mechanical and el... » read more

Fan-Out Packaging Gets Competitive


Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Blog Review: Aug. 17


Synopsys' Steve Pateras explains the basics of silicon lifecycle management and how it can help monitor, analyze, and optimize both semiconductor and end-user systems throughout the product value chain, from design and manufacturing to testing and maintenance. Siemens' Heather George considers the current state of 3D chiplet-based designs and efforts to standardize chiplet models and deliver... » read more

Challenges Grow For Modeling Auto Performance, Power


Rising complexity in automobiles is creating huge challenges about how to add more safety and comfort features and electronics into vehicles without reducing the overall range they can travel or pricing them so high that only the rich can afford them. While the current focus is on modeling hardware and software to understand interactions between systems, this remains a huge challenge. It req... » read more

AI Power Consumption Exploding


Machine learning is on track to consume all the energy being supplied, a model that is costly, inefficient, and unsustainable. To a large extent, this is because the field is new, exciting, and rapidly growing. It is being designed to break new ground in terms of accuracy or capability. Today, that means bigger models and larger training sets, which require exponential increases in processin... » read more

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