tag: Mentor

Why Safety-Critical Verification Is So Difficult
By Ann Mutschler - 15 Jul, 2020 - Comments: 0

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Blog Review: July 15
By Jesse Allen - 15 Jul, 2020 - Comments: 0

Synopsys' Mike Borza explains DARPA's Automatic Implementation of Secure Silicon (AISS) program and why prioritizing security in the chip development and manufacturing process is so important. Mentor's Jacob Wiltgen checks out how accurate early cycle safety analysis, aided by automation, can help avoid the problem of unmet safety goals and expensive later cycle iterations. Cadence's Paul... » read more

Maximizing Value Post-Moore’s Law
By Brian Bailey - 13 Jul, 2020 - Comments: 0

When Moore's Law was in full swing, almost every market segment considered moving to the next available node as a primary way to maximize value. But today, each major market segment is looking at different strategies that are more closely aligned with its individual needs. This diversity will end up causing both pain and opportunities in the supply chain. Chip developers must do more with a ... » read more

Easier Low Power ICs With Reference Flows
By Terence Chen - 09 Jul, 2020 - Comments: 0

By Terence Chen and Alexander Volkov Power-sensitive ICs for wearables and internet of things (IoT) products are in demand for markets ranging from automotive to military/aerospace to consumer. As with most ICs, cost and time-to-market pressures are important determiners of success. Reducing risk by using a vendor-created reference flow can confer a serious business advantage. Reference f... » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Designing For Extreme Low Power
By Brian Bailey - 09 Jul, 2020 - Comments: 3

There are several techniques available for low power design, but whenever a nanowatt or picojoule matters, all available methods must be used. Some of the necessary techniques are different from those used for high-end designs. Others have been lost over time because their impact was considered too small, or not worth the additional design effort. But for devices that last a lifetime on a si... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

Blog Review: July 8
By Jesse Allen - 08 Jul, 2020 - Comments: 0

Cadence's Paul McLellan profiles Alessandra Nardi, recipient of this year's Marie R. Pistilli Women in EDA award, how she entered the industry and her latest work on automotive and a functional safety language. In a video, Mentor's Colin Walls checks out why RISC-V is the hot new fashion in embedded systems development. A Synopsys writer explains why the MACsec security protocol is so imp... » read more

Chip Reliability Vs. Cost
By Ed Sperling - 05 Jul, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the cost, reliability and security with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. What follows are excerpts of that virtual conversation... » read more

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